- 26 7月, 2015 1 次提交
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由 Stefan Roese 提交于
This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de>
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- 17 7月, 2015 1 次提交
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- 15 7月, 2015 38 次提交
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由 Bin Meng 提交于
We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: NMatt Porter <mporter@konsulko.com> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NSimon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig' result so that the config option order matches Kconfig. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff, which is wrong for u-boot.rom components like u-boot-x86-16bit.bin. Change to use strtoll() so that it works on both 32-bit and 64-bit machines. Reported-by: NFei Wang <wangfei.jimei@gmail.com> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
To try to reduce the pain of confusion of binary blobs, add MD5 checksums for the current versions. This may worsen the situation as new versions appear, but it should still be possible to obtain these versions, and thus get a working setup. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Commit afbbd413 fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The layout of the ROM is a bit hard to discover by reading the code. Add a table to make it easier. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Enable a SPI environment and store it in a suitable place. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Simon Glass 提交于
The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NAndrew Bradford <andrew.bradford@kodakalaris.com>
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由 Simon Glass 提交于
The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Bin Meng 提交于
Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NJian Luo <jian.luo4@boschrexroth.de>
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由 Bin Meng 提交于
Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: NJian Luo <jian.luo4@boschrexroth.de> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Print the meaningful base address and mask of an MTRR range without showing the memory type encoding or valid bit. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Jian Luo 提交于
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: NJian Luo <jian.luo4@boschrexroth.de> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Jian Luo 提交于
We should allow pci config read/write to host bridge (b.d.f = 0.0.0) in the int1a_handler() which is a valid pci device. Signed-off-by: NJian Luo <jian.luo4@boschrexroth.de> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Jian Luo 提交于
PCI option rom may use different SS during its execution, so it is not safe to assume esp pointed to the same location in the protected mode. Signed-off-by: NJian Luo <jian.luo4@boschrexroth.de> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Enable writing MP table for Intel Crown Bay board. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Document U-Boot multi-processor support as well as configuration tables like SFI and MP tables for SMP OS kernel. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Implement write_mp_table() to create a minimal working MP table. This includes an MP floating table, a configuration table header and all of the 5 base configuration table entries. The I/O interrupt assignment table entry is created based on the same information used in the creation of PIRQ routing table from device tree. A check duplicated entry logic is applied to prevent writing multiple I/O interrupt entries with the same information. Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we need actually write the MP table at the F seg, just like we did for PIRQ routing and SFI tables. With MP table existence, linux kernel will switch to I/O APIC and local APIC to process all the peripheral interrupts instead of 8259 PICs. This takes full advantage of the multicore hardware and the SMP kernel. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
The MP table provides a way for the operating system to support for symmetric multiprocessing as well as symmetric I/O interrupt handling with the local APIC and I/O APIC. We provide a bunch of APIs for U-Boot to write the floating table, configuration table header as well as base and extended table entries. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Remove all the dead/unused macros from asm/ioapic.h. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
There is no need to populate multiple irq info entries with the same bus number and device number, but with different interrupt pin. We can use the same entry to store all the 4 interrupt pin (INT A/B/C/D) routing information to reduce the whole PIRQ routing table size. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
In fill_irq_info() pci device's function number is written into the table, however this is not really necessary. The function number can be anything as OS doesn't care about this field, neither does the PIRQ routing specification. Change to always writing 0 as the function number. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
We should write correct bus number to the PIRQ routing table for the irq router from device tree, instead of hard-coded zero. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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