- 26 1月, 2010 3 次提交
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由 Mike Frysinger 提交于
If you really want to slim down U-Boot and you would rather use a higher compression scheme (like LZMA), it'd be nice to disable gzip/zlib since these code bases take up a significant amount of space. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Stefano Babic 提交于
This patch adds support for "imximage" (MX Boot Image) to the mkimage utility. The imximage is used on the Freescales's MX.25, MX.35 and MX.51 processors. Further details under doc/README.imximage. This patch was tested on a Freescale mx51evk board. Signed-off-by: NStefano Babic <sbabic@denx.de>
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由 Detlev Zundel 提交于
Signed-off-by: NDetlev Zundel <dzu@denx.de>
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- 24 1月, 2010 2 次提交
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由 Detlev Zundel 提交于
Content of the RSR is put into gd early so we can output it together with the CPU info. The clearing of gd in board_init_f is redundant for this architecture as it is done in cpu_init_f so we remove it. Signed-off-by: NDetlev Zundel <dzu@denx.de>
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- 23 1月, 2010 20 次提交
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由 Daniel Gorsulowski 提交于
Normally the processor clock has a divisor of 2. In some cases this this needs to be set to 4. Check the user has set environment mdiv to 4 to change the divisor. Signed-off-by: NDaniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
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由 Vipin KUMAR 提交于
SPEAr320 SoC support contains basic spear320 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver - emi driver(cfi support) Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr310 SoC support contains basic spear310 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver - emi driver(cfi support) Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface Paraller NOR flashes. This patch adds the support for this IP The standard CFI driver is used to interface with NOR flashes Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr300 SoC support contains basic spear300 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
This patch adds the support to read and write mac id from i2c memory. For reading: if (env contains ethaddr) pick env ethaddr else pick ethaddr from i2c memory For writing: chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id in i2c memory Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr600 SoC support contains basic spear600 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr SoCs contain a synopsys usb device controller. USB Device IP can work in 2 modes - DMA mode - Slave mode The driver adds support only for slave mode operation of usb device IP. This driver is used along with standard USBTTY driver to obtain a tty interface over USB on the host Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP. Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr SoCs contain a synopsys i2c controller. This patch adds the driver for this IP. Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Vipin KUMAR 提交于
README.spear contains information about SPEAr architecture and build options etc Signed-off-by: NVipin <vipin.kumar@st.com>
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由 Tom Rix 提交于
Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 2045124ffd1a5e46d157349016a2c50f19c8c91d Signed-off-by: NTom Rix <Tom.Rix@windriver.com>
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由 Prafulla Wadaskar 提交于
As per coding guidlines, it is good to maintain proper ordering in the makefiles. This was missed during initial coding, corrected here. This was discovered during orion5x code review Thanks to Albert Aribaud for this. Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>
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由 Prafulla Wadaskar 提交于
These are few files directly imported from Linux kernel source. Those are not modifyed at all ar per strategy. These files contains source with GPLv2 only whereas u-boot expects GPLv2 or latter These files are updated for the same from prior permission from original writes Acked-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>
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由 Minkyu Kang 提交于
Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Seunghyeon Rhee 提交于
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases. Signed-off-by: NSeunghyeon Rhee <seunghyeon@lpmtec.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Stefan Roese 提交于
A newer CPLD version on the 405EX evaluation board requires a different EBC controller setup for the CPLD register access. This patch adds a CPLD version detection for Kilauea and code to reconfigure the EBC controller (chip select 2) for the old CPLD if no new version is found. Additionally the CPLD version is printed upon bootup: Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0) Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NWolfgang Denk <wd@denx.de> Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>
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由 Felix Radensky 提交于
The list of 4xx SoCs that should send type 1 PCI transactions is not defined correctly. As a result PCI-PCI bridges and devices behind them are not identified. The following 4xx variants should send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT. Signed-off-by: NFelix Radensky <felix@embedded-sol.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 22 1月, 2010 12 次提交
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由 Detlev Zundel 提交于
This is not only a cosmetic change as it fixes the real bug of board reset not working with the ELDK 4.2 toolchain. Signed-off-by: NDetlev Zundel <dzu@denx.de>
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由 Mike Frysinger 提交于
It's useful to be able to build up the host tools without having to select a board first. Pretty much all tools in there are config-independent anyways. Also add a shortcut "tools-all" to quickly build all host tools that are actually config-independent to allow for simple test builds. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Mike Frysinger 提交于
This code doesn't use any config.h defines, and the sha1.h header already declares a sha1_csum prototype. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Mike Frysinger 提交于
The u-boot command structures don't get used with host systems, so don't bother including it when building host code. This avoids an implicit need on config.h in the process. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Matthias Weisser 提交于
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>
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由 Wolfgang Denk 提交于
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由 Mike Frysinger 提交于
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Mike Frysinger 提交于
The sha1 code is currently compiled for everyone, but in reality, it's only used by the FIT code. So make it optional just like MD5. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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- 21 1月, 2010 2 次提交
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由 Felix Radensky 提交于
On platforms where SPD EEPROM and another EEPROM have adjacent I2C addresses SPD_EEPROM_ADDRESS should be defined as a single element array, otherwise DDR2 setup code would fail with the following error: ERROR: Unknown DIMM detected in slot 1 However, fixing SPD_EEPROM_ADDRESS would result in another error: ERROR: DIMM's DDR1 and DDR2 type can not be mixed. This happens because initdram() routine does not explicitly initialize dimm_populated array. This patch fixes the problem. Signed-off-by: NFelix Radensky <felix@embedded-sol.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Felix Radensky 提交于
Bootstrap options G and F are reported incorrectly (G instead of F and vice versa). This patch fixes this. Signed-off-by: NFelix Radensky <felix@embedded-sol.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 20 1月, 2010 1 次提交
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由 Shinya Kuribayashi 提交于
with a few adjustments for U-Boot. This fixes the following build error: make -C lib_generic/ zlib.c:31:27: error: asm/unaligned.h: No such file or directory zlib.c: In function 'inflate_fast': zlib.c:641: warning: implicit declaration of function 'get_unaligned' make[1]: *** [zlib.o] Error 1 make[1]: Leaving directory `/home/skuribay/git/u-boot.git/lib_generic' make: *** [lib_generic/libgeneric.a] Error 2 Reported-by: NHimanshu Chauhan <himanshu@symmetricore.com> Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
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