- 18 3月, 2016 3 次提交
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由 Przemyslaw Marczak 提交于
This reverts commit 71105f50. The reverted commit was applied for a temporary to unbreak few Exynos boards on the release. After the discussion about the change, this commit should be avoided. Fixed device-tree for Exynos, allows reverting it without any issues. Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: NSimon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Przemyslaw Marczak 提交于
This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: NSimon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org> Acked-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Simon Glass 提交于
Some controllers do not allow the output value to be read. Detect this and report the error in that case. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 17 3月, 2016 37 次提交
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由 Tom Rini 提交于
Since dhry_per_sec is a u64 we must also use lldiv here when working with it. Otherwise: ../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3' On some platforms. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Stefan Roese 提交于
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
At present samus reports about 5600 DMIPS. With the default iteration count this is OK, but if 10 million runs are performed it overflows. Fix it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
There is an extra line in the comment in the header. Remove it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a function to set the ID in the IOAPIC. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Update a few points which have become out-of-date. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This is a little easier on the eyes, particularly when the backlight is set to maximum. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add an address which can be used for loading and running the reference code when needed. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a video driver for Intel's broadwell integrated graphics controller. This uses a binary blob for most init, with the driver just performing a few basic tasks. This driver supports VESA as the mode-setting mechanism. Since most boards don't support driver model yet with VESA, a special case is added to the Kconfig for broadwell. Eventually all boards will use driver model and this can be removed. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a GPIO driver for the GPIO peripheral found on broadwell devices. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a driver for the broadwell low-power platform controller hub. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Make a few minor updates to make the meaning clearer. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Intel has invented yet another binary blob which firmware is required to run. This is run after SDRAM is ready. It is linked to load at a particular address, typically 0, but is a relocatable ELF so can be moved if required. Add support for this in the build system. The file should be placed in the board directory, and called refcode.elf. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Rather than setting up the pin configuration in the GPIO driver, use the new pinctrl driver to do it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
At present pin configuration on link does not use the standard mechanism, but some rather ugly custom code. As a first step to resolving this, add the pin configuration to the device tree. Four of the GPIOs must be available before relocation (for SDRAM pin strapping). Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Enable the microcode feature so that the microcode version is shown with the 'cpu detail' command. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
As each core starts up, record its microcode version and CPU ID so these can be presented with the 'cpu detail' command. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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