- 04 11月, 2011 2 次提交
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由 Heiko Schocher 提交于
similiar to commit dc7cd8e5, only adapted for the new spl framework. Signed-off-by: NHeiko Schocher <hs@denx.de> Acked-by: NTom Rini <trini@ti.com> Acked-by: NScott Wood <scottwood@freescale.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Fabio Estevam 提交于
Rename mc13783-rtc so that it can be used for both MC13783 and MC13892 PMICs. efikamx board, for example, does use a MC13892 PMIC, but the RTC selection is currently made as: #define CONFIG_RTC_MC13783 ,which is not very obvious. Let the MC13783 and MC13892 RTC be selected by: #define CONFIG_RTC_MC13XXX Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
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- 28 10月, 2011 4 次提交
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由 Kyle Moffett 提交于
As a part of the manufacturing process for some of our custom hardware, we are programming the EEPROMs attached to our Intel 82571EB controllers from software using U-Boot and Linux. This code provides several conditionally-compiled features to assist in our manufacturing process: CONFIG_CMD_E1000: This is a basic "e1000" command which allows querying the controller and (if other config options are set) performing EEPROM programming. In particular, with CONFIG_E1000_SPI this allows you to display a hex-dump of the EEPROM, copy to/from main memory, and verify/update the software checksum. CONFIG_E1000_SPI_GENERIC: Build a generic SPI driver providing the standard U-Boot SPI driver interface. This allows commands such as "sspi" to access the bus attached to the E1000 controller. Additionally, some E1000 chipsets can support user data in a reserved space in the E1000 EEPROM which could be used for U-Boot environment storage. CONFIG_E1000_SPI: The core SPI access code used by the above interfaces. For example, the following commands allow you to program the EEPROM from a USB device (assumes CONFIG_E1000_SPI and CONFIG_CMD_E1000 are enabled): usb start fatload usb 0 $loadaddr 82571EB_No_Mgmt_Discrete-LOM.bin e1000 0 spi program $loadaddr 0 1024 e1000 0 spi checksum update Please keep in mind that the Intel-provided .eep files are organized as 16-bit words. When converting them to binary form for programming you must byteswap each 16-bit word so that it is in little-endian form. This means that when reading and writing words to the SPI EEPROM, the bit ordering for each word looks like this on the wire: Time >>> ------------------------------------------------------------------ ... [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8], ... ------------------------------------------------------------------ (MSB is 15, LSB is 0). Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Ben Warren <biggerbadderben@gmail.com>
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由 Helmut Raiger 提交于
This renames BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT. Along the way it removes some leftover #define BOARD_LATE_INIT 1 and adds some basic documentation for board specific callbacks in README. Signed-off-by: NHelmut Raiger <helmut.raiger@hale.at> Acked-by: NStefano Babic <sbabic@denx.de>
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由 Wolfgang Denk 提交于
Add documentation for CONFIG_GATEWAYIP and CONFIG_NETMASK; also add information which environment variables are set. Signed-off-by: NWolfgang Denk <wd@denx.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 27 10月, 2011 6 次提交
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由 Donggeun Kim 提交于
In some cases, saving data in RAM as a file with FAT format is required. This patch allows the file to be written in FAT formatted partition. The usage is similar with reading a file. First, fat_register_device function is called before file_fat_write function in order to set target partition. Then, file_fat_write function is invoked with desired file name, start ram address for writing data, and file size. Signed-off-by: NDonggeun Kim <dg77.kim@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
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由 Simon Glass 提交于
This adds support for a new environment variable called 'fdtcontroladdr'. If defined, the hex address is used as the address of the control fdt for U-Boot. Note: I have not changed CONFIG_PRAM section as I already have an outstanding patch on that. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This adds support for an FDT to be build as a separate binary file called u-boot.dtb. This can be concatenated with the U-Boot binary to provide a device tree located at run-time by U-Boot. The Makefile is modified to provide this file in u-boot-dtb.bin. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This new option allows U-Boot to embed a binary device tree into its image to allow run-time control of peripherals. This device tree is for U-Boot's own use and is not necessarily the same one as is passed to the kernel. The device tree compiler output should be placed in the $(obj) rooted tree. Since $(OBJCOPY) insists on adding the path to the generated symbol names, to ensure consistency it should be invoked from the directory where the .dtb file is located and given the input file name without the path. This commit contains my entry for the ugliest Makefile / shell interaction competition. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This adds a device tree pointer to the global data. It can be set by board code. A later commit will add support for making a device tree binary blob available to U-Boot for run-time configuration. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This adds logic to tftp.c to implement the tftp 'put' command, and updates the README. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 22 10月, 2011 1 次提交
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由 Macpaul Lin 提交于
Documents and READMEs for NDS32 architecture. It patch also provides usage of SoC AG101 and board ADP-AG101. Signed-off-by: NMacpaul Lin <macpaul@andestech.com>
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- 18 10月, 2011 1 次提交
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由 Jason Hobbs 提交于
With these documented, we can start pushing towards standardizing their use across boards. Signed-off-by: NJason Hobbs <jason.hobbs@calxeda.com> Cc: Mike Frysinger <vapier@gentoo.org>
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- 10 10月, 2011 5 次提交
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由 Xiangfu Liu 提交于
Jz4740 is a multimedia application processor targeting for mobile devices like e-Dictionary, eBook, portable media player (PMP) and GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture provides high integration, high performance and low power consumption. JzRISC incorporated in Jz4740 is the advanced and power-efficient 32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K D-Cache, and can operate at speeds up to 400 MHz. On-chip modules such as LCD controller, embedded audio codec, multi- channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich suite of peripherals for multimedia application. NAND controller (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are also available. For more info about Ingenic XBurst Jz4740: http://en.ingenic.cn/eng/ http://www.linux-mips.org/wiki/Ingenic This patch introduces XBurst CPU support in U-Boot. It's compatible with MIPS32, but requires a bit different cache maintenance, timer routines, and boot mechanism using USB boot tool, so XBurst support can go into a separate new home, cpu/xburst/. Signed-off-by: NXiangfu Liu <xiangfu@openmobilefree.net> Acked-by: NDaniel <zpxu@ingenic.cn> Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
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由 York Sun 提交于
Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash. To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax: setenv ddr_interactive on After reset, U-boot prompts before initializing DDR controllers FSL DDR> The available commands are print print SPD and intermediate computed data reset reboot machine recompute reload SPD and options to default and recompute regs edit modify spd, parameter, or option compute recompute registers from current next_step to end next_step shows current next_step help this message go program the memory controller and continue with u-boot The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Che-liang Chiou 提交于
The 'time' command runs and reports execution time of commands. Sample usage: -------------------- u-boot# time crc 0x1000 1000 CRC32 for 00001000 ... 00001fff ==> ae94dc4b time: 0.004 seconds, 4 ticks -------------------- Signed-off-by: NChe-Liang Chiou <clchiou@chromium.org> Acked-by: NMike Frysinger <vapier@gentoo.org>
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由 Wolfgang Denk 提交于
Reported-by: NMichael Jones <michael.jones@matrix-vision.de> Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
Some previous changes added code right in the middle of the description of CONFIG_SHOW_BOOT_PROGRESS. Move this text down. Fix formatting while we are at it. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 06 10月, 2011 2 次提交
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由 Mike Frysinger 提交于
This is long over due. All but two net drivers have been converted, but those have now been dropped. The only thing left to do is actually delete all references to NET_MULTI and code that is compiled when that is not defined. So here we scrub the core code. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Graeme Russ 提交于
Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped.
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- 30 9月, 2011 1 次提交
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由 Timur Tabi 提交于
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 12 9月, 2011 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 03 8月, 2011 1 次提交
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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- 31 7月, 2011 1 次提交
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由 Daniel Schwierzeck 提交于
Amend section 'Directory Hierarchy' for current MIPS directory. Describe config options for MIPS. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: NThomas Langer <thomas.langer@lantiq.com> Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
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- 30 7月, 2011 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 28 7月, 2011 1 次提交
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由 Michael Jones 提交于
Signed-off-by: NMichael Jones <michael.jones@matrix-vision.de> Acked-by: NDetlev Zundel <dzu@denx.de>
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- 26 7月, 2011 3 次提交
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由 Mike Frysinger 提交于
For people who want to manually extract the embedded environment so that it can be manually packed into the final u-boot image, add a config opt to force building of the envcrc tool. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Aneesh V 提交于
replace all occurences of CONFIG_PRELOADER with CONFIG_SPL_BUILD Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Daniel Schwierzeck 提交于
Signed-off-by: NAneesh V <aneesh@ti.com> Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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- 17 7月, 2011 1 次提交
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由 Igor Grinberg 提交于
CONFIG_MACH_TYPE is used to set the machine type number in the common arm code instead of setting it in the board code. Boards with dynamically discoverable machine types can still set the machine type number in the board code. Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
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- 16 7月, 2011 2 次提交
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由 David A. Long 提交于
Add a new "fdt_high" enviroment variable. This can be used to control (or prevent) the relocation of the flattened device tree on boot. It can be used to prevent relocation of the fdt into highmem. The variable behaves similarly to the existing "initrd_high" variable. Signed-off-by: NDavid A. Long <dave.long@linaro.org>
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由 Yoshihiro Shimoda 提交于
Some Renesas SuperH have MMCIF module. This driver supports it. Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: NAndy Fleming <afleming@freescale.com>
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- 12 7月, 2011 1 次提交
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由 York Sun 提交于
We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 04 7月, 2011 2 次提交
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由 Aneesh V 提交于
PL310 is the L2$ controller from ARM used in many SoCs including the Cortex-A9 based OMAP4430 Add support for some of the key PL310 operations - Invalidate all - Invalidate range - Flush(clean & invalidate) all - Flush range Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: NAneesh V <aneesh@ti.com>
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- 02 7月, 2011 1 次提交
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由 Alex Waterman 提交于
This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: NAlex Waterman <awaterman@dawning.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 23 6月, 2011 1 次提交
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由 Wolfgang Denk 提交于
The 'trab' board configuration is broken, and there is nobody who is interested and willing to fix it. Drop it. This includes support for VFD displays which have always been used by this board only. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 20 5月, 2011 2 次提交
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由 Kumar Gala 提交于
We assumed that only a small set of compatiable strings would be needed to find the PCIe device tree nodes to be fixed up. However on newer platforms the simple rules no longer work. We need to allow specifying the PCIe compatiable string for each individual SoC. We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if the default isn't sufficient. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Luca Ceresoli 提交于
Signed-off-by: NLuca Ceresoli <luca.ceresoli@comelit.it> Cc: Wolfgang Denk <wd@denx.de> Acked-by: NDetlev Zundel <dzu@denx.de>
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