- 27 7月, 2020 5 次提交
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由 Xiaowei Bao 提交于
Add the PCIe EP mode support for lx2160a-v2 platform. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Xiaowei Bao 提交于
Modify the ls_pcie_dump_atu function, make it can print the INBOUND windows registers. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Xiaowei Bao 提交于
Add the INBOUND configuration for VFs of PF. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Xiaowei Bao 提交于
Add the multiple function support for Layerscape platform, some PEXs of Layerscaple platform have more than one PF. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Xiaowei Bao 提交于
Split the RC and EP driver, and reimplement the EP driver base on the EP framework. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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- 26 12月, 2019 1 次提交
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由 Wasim Khan 提交于
Add stream_id_cur field to ls_pcie structure and initialize it with 0 for all pcie controllers. This field will be used for streamId calculation. Signed-off-by: NWasim Khan <wasim.khan@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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- 18 1月, 2019 1 次提交
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由 Xiaowei Bao 提交于
Modify the RC and EP mode judge method, save the mode as a variable, the variable will be used by other function. Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 07 5月, 2018 1 次提交
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由 Tom Rini 提交于
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 22 9月, 2017 1 次提交
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由 Tuomas Tynkkynen 提交于
This field is no longer used since the DM conversion. Drop it. Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 01 8月, 2017 1 次提交
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由 Santan Kumar 提交于
Update SVR as per the SOC document. -LS2081A: 0x870919 -> 0x870918 -LS2041A: 0x870915 -> 0x870914 Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 24 5月, 2017 1 次提交
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由 Priyanka Jain 提交于
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NSantan Kumar <santan.kumar@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 29 3月, 2017 2 次提交
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由 Hou Zhiqiang 提交于
The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 19 1月, 2017 3 次提交
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由 Minghuan Lian 提交于
All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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