The explicit arch specific build symbol allows to group supported
boards, generalize common config options and it will serve as
a dependency for platform only drivers.

Two related board defconfigs are resynced after the change.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

This patch enables the cache command, mostly for convenience of testing.
Signed-off-by: NHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>

This patch removes 'console=' argument, because kernel uses
stdout-path as parameter.
Signed-off-by: NHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>

Simplify defconfig for ZynqMP but keep option not to enable it for mini
targets.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Virtual QEMU board is generating DTB self and putting it to
VERSAL_QEMU_DTB_ADDR address.
Board is using CONFIG_OF_BOARD which ensures that u-boot is aligned with
board created by QEMU.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Ethernet is not present on this board that's why there are two other
options how to wire the board to ethernet. The first is asix_eth usb
host converter which is already enabled by default. The second option is
to use USB CDC/RNDIS ethernet gadget.

This patch is enabling CDC which is working with Linux.
With new bind/unbind command there is no need to call usb_ether_init()
from platform code and use for example these commands:

bind /amba/usb0@ff9d0000/dwc3@fe200000 usb_ether
dhcp
unbind /amba/usb0@ff9d0000/dwc3@fe200000
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There are some inconsistencies which should be fixed.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable loading FPGA from FIT image in SPL.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

That's what we'll have in production.
But note it won't work for loading via JTAG as
eFlash is not directly writable, one needs to use
prebootloader to flash uboot.bin from SD-card into eFlash.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

There's no Ethernet controller on the board so no point in having
networking support. This also saves us 5.5 kB of precious memory.

| # bloat-o-meter u-boot.net u-boot.no_net_regex | tail -1
| Total: Before=127892, After=122334, chg -4.35%
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

This adds platform code for the Khadas VIM2 board based on a
Meson GXM (S912) SoC with the Meson GXM configuration.

This initial submission supports UART, MMC/SDCard and Ethernet.
USB is partially supported.

All the code is from Neil Armstrong! I just rebased the code, do
some cleanup and tested on my board.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLoic Devulder <ldevulder@suse.de>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>

This patch add SPL DM support for da8xxevm boards
with SPL serial, SPI drivers supported via platdata.

Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850evm

Add Kconfig options so that the RTC can be used in SPL and TPL. This is
helpful for accessing the contents of CMOS RAM, for example.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up the two boards which use it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add support for the debug UART so that sandbox provides build testing for
this feature.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present to output a log message you need something like:

   log(UCLASS_SPI, LOCL_INFO, "message1");
   log(UCLASS_SPI, LOCL_INFO, "message2");

but many files use the same category throughout. Also it is helpful to
shorten the length of log names, providing helpers for common logging
levels. Add some macros so that it is possible to do:

   (top of file, before #includes)
   #define LOG_CATEGORY UCLASS_SPI

   (later in the file)
   log_info("message1");
   log_debug("message2");
   log_err("message3");
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enables cmd_avb and its dependencies need to run the AVB tests.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJens Wiklander <jens.wiklander@linaro.org>
[trini: Disable for sandbox_noblk]
Signed-off-by: NTom Rini <trini@konsulko.com>

With the device trees doing most of the work of pin-muxing and
DM doing much of the peripheral initialization, this creates
new defconfig files for each of the Logic PD variants with
proper register settings/pin-muxing.
Signed-off-by: NAdam Ford <aford173@gmail.com>
[trini: Update MAINTAINERS entry]
Signed-off-by: NTom Rini <trini@konsulko.com>

The DesignWare ARC IoT Development Kit is a versatile platform
that includes the necessary hardware and software to accelerate
software development and debugging of sensor fusion,
voice recognition and face detection designs.

More information is avaialble here [1] and here [2].

The board is based on real silicon with
ARC EM9D-based Data Fusion IP Subsystem.

It sports a rich set of I/O including
 * DW USB OTG
 * DW MobileStorage (used for micro SD-card)
 * GPIO
 * multiple serial interface including DW APB UART
 * ADC, PWM and eFlash, SRAM and SPI Flash memory
 * Real-Time Clock (RTC)
 * Bluetooth module with worldwide regulatory compliance
   (FCC, IC, CE, ETSI, TELEC)
 * On-board 9-axis sensor (gyro, accelerometer and compass)

Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18
extension header.

One of the most interesting features for developers is built-in
Digilent USB JTAG probe so only micro-USB cable is needed!

[1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit
[2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdfSigned-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

This implies DM support for some common drivers that are used on
RISC-V.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

RISC-V is a pretty new architecture and should support DM and
OF_CONTROL by default.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

Enable USB PHY driver.
Also fixed the alphabetically ordering of the config.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

Add tests for the new board uclass.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMario Six <mario.six@gdsys.cc>

With DM enabled, this patch enables DM_SERIAL and removes
the NS16550 initialization from da850_lowlevel since the driver
will take care of that itself.
Signed-off-by: NAdam Ford <aford173@gmail.com>

With DM_I2C and DM_GPIO working, this patch can enable the
GPIO expander on the I2C bus.  This GPIO expander is connected
to some of the DIP switches and can now read the status of these
pins.
Signed-off-by: NAdam Ford <aford173@gmail.com>

The simple pin controller works for da850, so this patch enables
this to pin-mux the pins defined in the device tree for the da850evm.
Signed-off-by: NAdam Ford <aford173@gmail.com>

With DM enabled, this patch enables the 'dm' command to access
the dm tree, uclass and devres.
Signed-off-by: NAdam Ford <aford173@gmail.com>

The simple pinctrl driver currently available works with the omap3.
Enabling this will use the device tree to automatically set the
pin-muxing for various drivers.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Add commands for fdt overlay merging. This is required for the boot scripts
that detect PDAs and apply specific overlays to the DTB passed on to kernel.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Add commands for fdt overlay merging. This is required for the boot scripts
that detect PDAs and apply specific overlays to the DTB passed on to kernel.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Add commands for fdt overlay merging. This is required for the boot scripts
that detect PDAs and apply specific overlays to the DTB passed on to kernel.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Add commands for fdt overlay merging. This is required for the boot scripts
that detect PDAs and apply specific overlays to the DTB passed on to kernel.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Add commands for fdt overlay merging. This is required for the boot scripts
that detect PDAs and apply specific overlays to the DTB passed on to kernel.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

SAMA5D4 SoC can have extra clip boards (PDAs) connected, which have
an EEPROM memory for identification. A special GPIO can be used to read
this memory over 1wire protocol.
Enabling one wire and eeprom drivers for this memory.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

SAMA5D2 SoC can have extra clip boards (PDAs) connected, which have
an EEPROM memory for identification. A special GPIO can be used to read
this memory over 1wire protocol.
Enabling one wire and eeprom drivers for this memory.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

SAMA5D2 SoC can have extra clip boards (PDAs) connected, which have
an EEPROM memory for identification. A special GPIO can be used to read
this memory over 1wire protocol.
Enabling one wire and eeprom drivers for this memory.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>