When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>

For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>

For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>

This document describes the implementation of the boot from SRIO,
includes the introduction of envionment, an example based on P4080DS
platform, an example of the slave's RCW, and the description about
how to use this feature.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

When defined CONFIG_ENV_IS_NOWHERE, there will be some
compilation errors:

./common/env_nowhere.o: In function `env_relocate_spec':
./common/env_nowhere.c:38: multiple definition of `env_relocate_spec'
./common/env_flash.o: ./common/env_flash.c:326: first defined here
./common/env_nowhere.o: In function `env_get_char_spec':
./common/env_nowhere.c:42: multiple definition of `env_get_char_spec'
./common/env_flash.o:./common/env_flash.c:78: first defined here
./common/env_nowhere.o: In function `env_init':
./common/env_nowhere.c:51: multiple definition of `env_init'
./common/env_flash.o:./common/env_flash.c:237: first defined here
make[1]: *** [./common/libcommon.o] Error 1
make[1]: Leaving directory `./common'
make: *** [./common/libcommon.o] Error 2

Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

Rewrite this struct for the support of two ports and two message
units registers.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

Currently "u-boot", the elf file generated via u-boot-nand.lds does not
contain required debug information i.e. .debug_{line, info, abbrev, aranges,
ranges} into their respective _global_ sections.

The original ld script line arch/powerpc/cpu/mpc85xx/start.o
KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
not process start.o again for bootpg.

So Fix u-boot-nand.lds to generate these debug information.
Signed-off-by: NAnmol Paralkar <b07584@freescale.com>
Signed-off-by: NJohn Russo <John.Russo@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add env in NAND support when boot from NAND.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

New P2041RDB board will add a NAND chip, so add support for NAND and
NAND boot.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

NAND SPL code never compile the vector table.
So no need to setup interrupt vector table for NAND SPL.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.

As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00  hard-coded values.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

For e500 and e500v2 architecturees processor IVPR address should be alinged on
64K boundary.

in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
not point to an exception handler.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.

Default device tree nor and nand node should have the following structure:

	Example:

		nor_flash: nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x02000000>;
			bank-width = <2>;
			device-width = <1>;
			status = "okay";

			partition@0 {
				label = "ramdisk";
				reg = <0x00000000 0x01c00000>;
			};
		}

		nand_flash: nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1023-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x00040000>;
			status = "disabled";

			u-boot-nand@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				read-only;
			};
		}

When booting from nor flash, the status of nor node is enabled and the
status of nand node is disabled in the default dts file, so do not do
anything.

But, when booting from nand flash, need to do some operations:

	o Disable the NOR node by setting status = "disabled";
	o Enable the NAND node by setting status = "okay";
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Now that run_command() handles both parsers, clean up sandbox to use it.
This fixes a build error.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NMike Frysinger <vapier@gentoo.org>

Commit 0a672d49 "arm: Add Prep subcommand support to bootm" re-organized
do_bootm_linux for ARM. During the re-organization, the call to
fdt_fixup_ethernet() was removed. I assume this was useful, so add it
back.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NTom Rini <trini@ti.com>

Commit 0a672d49 "arm: Add Prep subcommand support to bootm" re-organized
do_bootm_linux() for ARM. During the re-organization, the code to pass
the device tree to the kernel was removed. Add it back. This restores
the ability to boot a kernel using device tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NTom Rini <trini@ti.com>
Acked-by: NAllen Martin <amartin@nvidia.com>
Tested-by: NAllen Martin <amartin@nvidia.com>

If one command fails, 'run' command should terminate and not execute
any remaining variables.
Signed-off-by: NTimo Ketola <timo@exertus.fi>
Tested-by: NWolfgang Denk <wd@denx.de>
Tested-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Also tiny style cleanup to tools/patman/README
Signed-off-by: NWolfgang Denk <wd@denx.de>

... after commit "net/miiphy/serial: drop duplicate NAMESIZE
define" (sha1:f6add132) was applied. The building of the new
LL TEMAC network driver fails with error below:

xilinx_ll_temac.c: In function 'xilinx_ll_temac_initialize':
xilinx_ll_temac.c:301: error: 'NAMESIZE' undeclared (first use in this function)
xilinx_ll_temac.c:301: error: (Each undeclared identifier is reported only once
xilinx_ll_temac.c:301: error: for each function it appears in.)
Signed-off-by: NStephan Linz <linz@li-pro.net>
Acked-by: NMike Frysinger <vapier@gentoo.org>

What is this?

=============

This tool is a Python script which:
- Creates patch directly from your branch
- Cleans them up by removing unwanted tags
- Inserts a cover letter with change lists
- Runs the patches through checkpatch.pl and its own checks
- Optionally emails them out to selected people

It is intended to automate patch creation and make it a less
error-prone process. It is useful for U-Boot and Linux work so far,
since it uses the checkpatch.pl script.

It is configured almost entirely by tags it finds in your commits.
This means that you can work on a number of different branches at
once, and keep the settings with each branch rather than having to
git format-patch, git send-email, etc. with the correct parameters
each time. So for example if you put:

in one of your commits, the series will be sent there.

See the README file for full details.
END
Signed-off-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NJens Scharsig <js_at_ng@scharsoft.de>

Fix the warning

mmc.c: In function 'mmc_send_cmd':
mmc.c:87: warning: assignment from incompatible pointer type

in case CONFIG_MMC_TRACE is enabled.
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
CC: Andy Fleming <afleming@freescale.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NMarek Vasut <marex@denx.de>

This is just a patch for the problem reported here:
http://lists.denx.de/pipermail/u-boot/2012-February/117580.html originally reported by Igor.

"Looks like this is copy paste error from my side,(for port2/3 it should have been bypass
 for port2/3 rather its port1 set in bypass mode)"

I only submit the patch since it is missing in 2012.04-rc3 while the twister board
depends on it. Maybe it is already somewhere in the reposistory, but I cannot find it.

note: the twister boards still needs an additional `usb reset`, don't know why.

U-Boot 2012.04-rc3-dirty (Apr 19 2012 - 21:38:38)

AM35XX-GP ES1.0, CPU-OPP2, L3-165MHz, Max CPU Clock 600 Mhz
TAM3517 TWISTER Board + LPDDR/NAND
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0
In:    serial
Out:   serial
Err:   serial
Die ID #746c0000000000000155dc1405011024
Net:   DaVinci-EMAC, smc911x-0
Hit any key to stop autoboot:  0
twister => usb start
(Re)start USB...
USB:   Register 1313 NbrPorts 3
USB EHCI 1.00
scanning bus for devices... 1 USB Device(s) found
       scanning bus for storage devices... 0 Storage Device(s) found
twister => usb reset
(Re)start USB...
USB:   Register 1313 NbrPorts 3
USB EHCI 1.00
scanning bus for devices... 1 USB Device(s) found
       scanning bus for storage devices... 0 Storage Device(s) found
twister => usb reset
(Re)start USB...
USB:   Register 1313 NbrPorts 3
USB EHCI 1.00
scanning bus for devices... 1 USB Device(s) found
       scanning bus for storage devices... 0 Storage Device(s) found
twister => usb reset
(Re)start USB...
USB:   Register 1313 NbrPorts 3
USB EHCI 1.00
scanning bus for devices... 1 USB Device(s) found
       scanning bus for storage devices... 0 Storage Device(s) found
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Govindraj.R <govindraj.raja <at> ti.com>
Acked-by: NTom Rini <trini@ti.com>

Current versions of  dtc  always print a message like

	DTC: dts->dtb  on file "dt.dtb.tmp"

which cannot even be suppressed with "-qqq".  To avoid incorrect
MAKEALL status, we manually filter out this message.  This is a bit
complicated, as we have to make sure to set a correct return code.

Also, get rid of the temp file: dtc accepts "-" for stdin.
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Fix: FATAL ERROR: Couldn't open "../arch/arm/dts/tegra20.dtsi": No
such file or directory
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Fix gcc 4.6 build warnings:
onenand_base.c: In function 'onenand_probe':
onenand_base.c:2577:6: warning: variable 'maf_id' set but not used
[-Wunused-but-set-variable]
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

* 'master' of git://git.denx.de/u-boot-sh:
  sh: ecovec: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  sh: Fix rsk7264 pin setup for on-board ethernet

When calling board_late_init, we need to define CONFIG_BOARD_LATE_INIT.
The latest ecovec config defines BOARD_LATE_INIT, board_late_init is not called.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This sets up the external ethernet IRQ pin.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Do the same AXI cache and Qos settings done already in the
SabreLite imximage.cfg for the ARM2 board, too.

It fixes a display flash issue caused by low priority of
the display IDMA channel.
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
Acked-by: NJason Liu <r64343@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

* 'master' of git://git.denx.de/u-boot-arm:
  ARM926EJS: Fix cache.c to comply with checkpatch.pl
  ARM926EJS: Make asm routines volatile in cache ops
  MX35: mx35pdk: wrong board revision
  ARM1136: MX35: Make asm routines volatile in cache ops
  ARM: add u-boot.imx as target for i.MX SOCs
  M28: Pull out CONFIG_APBH_DMA so it's always enabled
  DMA: Split the APBH DMA init into block and channel init
  imx: Return gpio_set_value in gpio_direction_output
  imx: Use GPIO_TO_PORT macro in the gpio driver instead of (gpio >> 5)
  imx: Add GPIO_TO_PORT macro in the mxc_gpio driver
  imx: Remove unneeded/repititive definitions from imx headers
  i.MX28: Allow coexistence of PIO and DMA mode for SD/MMC
  MX31: mx31pdk: drop enable_caches from board file
  i.MX28: Fix initial stack pointer position
  mx35: mx35pdk: fix when cache functions are linked
  mx35: flea3: fix when cache functions are linked
  ARM: 926ejs: use debug() for misaligned addresses
  ARM1136: add cache flush and invalidate operations
  mx6qsabrelite: Fix the serial console port
  mx6qsabrelite: Add boot switch setting information into the README
  i.MX6: mx6qsabrelite: add cache commands if cache is enabled
  i.MX6: implement enable_caches()
  i.MX6: define CACHELINE_SIZE
  MX53: DDR: Fix ZQHWCTRL field TZQ_CS
  mx28evk: Add a README file
  mx28: Split the README into a common part and a m28 specific part
  tricorder: Load kernel from ubifs
  tricorder: Add UBIFS
  cm-t35: fix Ethernet reset timing
  hawkboard: Add CONFIG_SPL_LIBGENERIC_SUPPORT
  BeagleBoard: Remove userbutton command and use gpio command instead
  OMAP: Move omap1510inn to Unmaintained / Orphaned

Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

We certainly don't want the compiler to reorganise the code for dcache flushing.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: NMike Frysinger <vapier@gentoo.org>
Acked-by: NStefano Babic <sbabic@denx.de>

The board revision is detected accessing to the pmic,
that is not available before relocation (I2C).
This generates the following error:

CPU:   Freescale i.MX35 rev 2.0 at 532 MHz.
Reset cause: WDOG
<reg num> = 7 is invalid. Should be less than 0
Board: MX35 PDK 1.0

The revision number is wrong, as a default value is printed
(tested on a mx35pdk Rev. 2.0).

Move the output in the board_late_init(), when
pmic can be accessed.
Signed-off-by: NStefano Babic <sbabic@denx.de>

As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>

Freescale SOCs require an header to u-boot.bin

The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).
Signed-off-by: NStefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Loïc Minier <loic.minier@linaro.org>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: NMike Frysinger <vapier@gentoo.org>
Acked-by: NDirk Behme <dirk.behme@de.bosch.com>
Tested-by: NDirk Behme <dirk.behme@googlemail.com>

The ABPH DMA is now used also by the SD card. Therefore it has to be enabled
even if NAND is disabled.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>