The callee (arch/arm/lib/cache-cp15.c) has a #ifdef
CONFIG_SYS_DCACHE_OFF conditional.  The same conditional in the
caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The L2 cache is used as a temporary SRAM on SPL.
Now the secondary CPUs store the necessary code for jumping to
Linux on their L1 I-caches.  So, the L2 cache can be disabled
much earlier, at the very entry of U-Boot proper (lowlevel_init).
This makes the boot sequence clearer.
Also, as the L1 cache has been disabled by the start.S,
enable_caches() does not need to do it again.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, the secondary CPU(s) are kicked three times:
Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux.
It makes the boot sequence very complicated.

This commit merges the first and the second kicks, so the secondary
CPU(s) can directly jump from SPL to Linux.
arch/arm/mach-uniphier/smp.S is no longer necessary.

Linux boot test passed.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since commit 0e7368c6 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Move
arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/*
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

These are used by Panasonic UniPhier SoC family.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>