- 09 8月, 2021 40 次提交
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由 Peng Fan 提交于
Disable wdog3 which is configured by ROM Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
SRAM2 is half L2 cache and default to SRAM after system boot. To enable the full l2 cache (512KB), it needs to reset A35 to make the change happen. So re-implement the jump entry function in SPL: 1. configure the core0 reset vector to entry (ATF) 2. enable the L2 full cache 3. reset A35 So when core0 up, it runs into ATF. And we have 512KB L2 cache working. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
CMC1 also has a MR register for bootcfg Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Peng Fan 提交于
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add i.MX8ULP clock support Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
i.MX8ULP lpuart has same register layout as i.MX7ULP and i.MX8 Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Add pinctrl driver for i.MX8ULP Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Support i.MX8ULP in fec_mxc Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Ye Li 提交于
Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Peng Fan 提交于
Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig public to both. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
i.MX8ULP support using ROM API to load container image, it use same ROM API as i.MX8MN/MP, and use same container format as i.MX8QM/QXP. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure for i.MX8ULP Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Since the container is shared among i.MX platforms, move its header file to mach-imx Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Since we will re-use the container parser on imx8ulp, move the codes to mach-imx Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Peng Fan 提交于
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add get reset cause function to show what triggerred reset. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Support print cpu info. the clock function has not been added, it will be added in following patches. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
These defines could be reused by i.MX8ULP, so move them to common header. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add i.MX8ULP cpu type and helpers. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Tim Harvey 提交于
Add the specific board model from EEPROM config to the device-tree to make it easier to access from Linux userspace. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
remove unused SPL features to shink the size of the SPL which otherwise would no longer fit into IMX8M Mini OCRAM. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Fabio Estevam 提交于
Make the conversion to driver model as it is mandatory. Successfully tested booting Linux from the SD card. Dropped support for networking and splash screen as these need to be properly converted to DM and tested. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Sebastian Reichel 提交于
Add PCIe reset gpio to the Bx50v3 devicetree and get get rid of CONFIG_PCIE_IMX_PERST_GPIO. Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.com>
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由 Fabio Estevam 提交于
Select CONFIG_IMX_HAB so that the "hab_status" command becomes available, which is useful for checking if the chip has been correctly setup to run in secure boot mode. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Tim Harvey 提交于
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Do the following to add support for it: - add dts - add PMIC config Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Add board model/serial# strings to env. Move the creation of the strings to gsc_read() and the display of the info into gsc_info() so they are available to U-Boot proper. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
replace looking up i2c bus name by bus number and define bus numbers and eeprom address with #defines. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Get mem size from dt which SPL updated per EEPROM config. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Use the common imx8mm-u-boot.dtsi Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties not supported by U-Boot drivers/net/phy/dp83867.c with the proper 'ti,fifo-depth' property. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12 is the power-enable to the TPS25821 Source controller and power switch responsible for monitoring the CC pins and enabling VBUS. Therefore GPIO1_12 must always be enabled and the vbus output enable from the IMX8MM can be ignored. To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the TPS25821 and change the regulator output to GPIO1_10 which is unconnected. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Fabio Estevam 提交于
The intention of commit d714a75f ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB") was to convert from CONFIG_SECURE_BOOT to CONFIG_IMX_HAB, but it replaced with an extra "_" character. Fix it by using the correct CONFIG_IMX_HAB symbol. Fixes: d714a75f ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB") Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Tim Harvey 提交于
The GW54xx-G revision has the foolowing changes: - replaces the EOL GbE PHY with an updated part (requires an enable pin) - replaces the EOL analog video decoder with an updated part (requires dt prop) - add power control to miniPCIe socket Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW53xx-G revision has the foolowing changes: - replaces the EOL GbE PHY with an updated part (requires an enable pin) - replaces the EOL analog video decoder with an updated part (requires dt prop) - add power control to miniPCIe socket Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW5913 is a Single Board Computer based on the NXP i.MX6Q/DL SoC with the following features: - DDR3 DRAM - NAND FLASH (256MiB or 2048MiB) - Gateworks System Periperhal Controller - front panel LED's - front panel pushbutton - Digital I/O connector (I2C/GPIO/UART) - u-blox Zoe-M8Q GPS - 1x RJ45 GbE - 1x MiniPCIe socket with PCIe USB 2.0 and nanoSIM socket - Passive PoE and wide-range DC power supply Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW5912 is a Single Board Computer based on the NXP i.MX6Q/DL SoC with the following features: - DDR3 DRAM - NAND FLASH (256MiB or 2048MiB) - microSD socket - Gateworks System Periperhal Controller - front panel LED's - front panel pushbutton - RS232 connector (2x UARTs) - CAN/RS485 connector - Digital I/O connector (I2C/GPIO) - SPI connector - u-blox Zoe-M8Q GPS - LIS2DE12 Accellerometer - 1x FEC GbE RJ45 with 802.3at Active PoE - 1x PCI GbE RJ45 with Passive PoE - 5x MiniPCIe socket with PCIe/USB 2.0 - 1x MiniPCIe socket with PCIe/USB 2.0 and SIM socket - Aux power input with wide-range DC power supply Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW5910 is a Single Board Computer based on the NXP i.MX6Q/DL SoC with the following features: - DDR3 DRAM - NAND FLASH (256MiB or 2048MiB) - microSD socket - Gateworks System Periperhal Controller - front panel LED's - front panel pushbutton - RS232 connector (2x UARTs) - Digital I/O connector (I2C/GPIO) - SPI connector - u-blox Zoe-M8Q GPS - LIS2DE12 Accellerometer - TI CC1352 ARM Cortex-M4 multiprotocol sub-1GHz / 2.4GHz wireless MCU - On-board brcmfmac WiFi and BT module - RGMII RJ45 GbE - 1x MiniPCIe socket with PCIe/USB 2.0 - 1x MiniPCIe socket with USB 2.0 and nanoSIM socket - Passive PoE and wide-range DC power supply Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Use dt-bindings for GSC hwmon devices. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Flexcan pinmux is configured in kernel dt. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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