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  1. 21 6月, 2013 1 次提交
  3. 08 6月, 2013 1 次提交
    • G
      pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option · 842033e6
      由 Gabor Juhos 提交于 
      The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
      842033e6
  5. 25 5月, 2013 3 次提交
  7. 31 1月, 2013 3 次提交
  9. 23 10月, 2012 2 次提交
  11. 16 10月, 2012 1 次提交
  13. 24 8月, 2012 1 次提交
  15. 23 8月, 2012 5 次提交
    • S
      powerpc/CoreNet: add tool to support pbl image build. · 5d898a00
      由 Shaohui Xie 提交于 
      Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      5d898a00
    • L
      powerpc/corenet_ds: Slave module for boot from PCIE · 461632bd
      由 Liu Gang 提交于 
      When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE interface, so it can not modify the ENV parameters stored
	  in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE interface by RCW.
	3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
	1. Updated the README.srio-boot-corenet to add descriptions about
	   boot from PCIE, and change the name to
	   README.srio-pcie-boot-corenet.
	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
	   from PCIE.
	3. Updated other macros and documents if needed to add information
	   about boot from PCIE.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      461632bd
    • L
      powerpc/corenet_ds: Master module for boot from PCIE · b5f7c873
      由 Liu Gang 提交于 
      For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      b5f7c873
    • L
      powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro · 81fa73ba
      由 Liu Gang 提交于 
      When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      81fa73ba
    • L
      powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target · ff65f126
      由 Liu Gang 提交于 
      Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      ff65f126
  17. 09 8月, 2012 2 次提交
  19. 07 7月, 2012 1 次提交
  21. 21 6月, 2012 1 次提交
  23. 25 4月, 2012 6 次提交
    • L
      powerpc/corenet_ds: Slave core in holdoff when boot from SRIO · 5056c8e0
      由 Liu Gang 提交于 
      When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.

Master needs to:
	1. Set outbound SRIO windows in order to configure slave's registers
	   for the core's releasing.
	2. Check the SRIO port status when release slave core, if no errors,
	   will implement the process of the slave core's releasing.
Slave needs to:
	1. Set all the cores in holdoff by RCW.
	2. Be powered on before master's boot.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      5056c8e0
    • L
      powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO · 0a85a9e7
      由 Liu Gang 提交于 
      When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.

NOTE: Because the slave can not erase, write master's NOR flash by SRIO
	  interface, so it can not modify the ENV parameters stored in
	  master's NOR flash using "saveenv" or other commands.

Master needs to:
	1. Put the slave's ENV into it's own memory space.
	2. Set an inbound SRIO window covered slave's ENV stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      0a85a9e7
    • L
      powerpc/corenet_ds: Slave uploads ucode when boot from SRIO · 3f1af81b
      由 Liu Gang 提交于 
      When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      3f1af81b
    • L
      powerpc/corenet_ds: Slave module for boot from SRIO · 292dc6c5
      由 Liu Gang 提交于 
      For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      292dc6c5
    • L
      powerpc/corenet_ds: Master module for boot from SRIO · 5ffa88ec
      由 Liu Gang 提交于 
      For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      5ffa88ec
    • L
      powerpc/corenet_ds: Correct the compilation errors about ENV · fd0451e4
      由 Liu Gang 提交于 
      When defined CONFIG_ENV_IS_NOWHERE, there will be some
compilation errors:

./common/env_nowhere.o: In function `env_relocate_spec':
./common/env_nowhere.c:38: multiple definition of `env_relocate_spec'
./common/env_flash.o: ./common/env_flash.c:326: first defined here
./common/env_nowhere.o: In function `env_get_char_spec':
./common/env_nowhere.c:42: multiple definition of `env_get_char_spec'
./common/env_flash.o:./common/env_flash.c:78: first defined here
./common/env_nowhere.o: In function `env_init':
./common/env_nowhere.c:51: multiple definition of `env_init'
./common/env_flash.o:./common/env_flash.c:237: first defined here
make[1]: *** [./common/libcommon.o] Error 1
make[1]: Leaving directory `./common'
make: *** [./common/libcommon.o] Error 2

Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
      fd0451e4
  25. 12 2月, 2012 1 次提交
  27. 29 11月, 2011 2 次提交
    • S
      powerpc/p3060qds: Add board related support for P3060QDS platform · ae6b03fe
      由 Shengzhou Liu 提交于 
      The P3060QDS is a Freescale reference board for the six-core P3060 SOC.

P3060QDS Board Overview:
 Memory subsystem:
  - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
  - 128M Bytes NOR flash single-chip memory
  - 16M Bytes SPI flash
  - 8K Bytes AT24C64 I2C EEPROM for RCW
 Ethernet:
  - Eight Ethernet controllers (4x1G + 4x1G/2.5G)
  - Three VSC8641 PHYs on board (2xRGMII + 1xMII)
  - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
 PCIe: Two PCI Express 2.0 controllers/ports
 USB:  Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
 I2C:  Four I2C controllers
 UART: Supports two dUARTs up to 115200 bps for console
 RapidIO:  Two RapidIO, sRIO1 and sRIO2
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      ae6b03fe
    • T
      powerpc/85xx: clean up and document the QE/FMAN microcode macros · f2717b47
      由 Timur Tabi 提交于 
      Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both.  A given SOC will only have
a QE or an Fman, so this is safe.

Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND.  There's no way to know by looking at a variable how it's supposed
to be used.

In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      f2717b47
  29. 22 10月, 2011 2 次提交
  31. 06 10月, 2011 1 次提交
  33. 03 10月, 2011 2 次提交
    • K
      powerpc/85xx: Refactor some defines out of corenet_ds.h · c6d33901
      由 Kumar Gala 提交于 
      Move some SoC/board specific defines out of corenet_ds.h and into the
corresponding P3041DS/P4080DS/P5020.h.

We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060
SoC/reference board does not have these devices and it will share the same
board code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      c6d33901
    • R
      powerpc/p4080: Add support for secure boot flow · 7065b7d4
      由 Ruchika Gupta 提交于 
      Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
   (Please note that ISBC expects all these addresses, images to be
    validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
   at 0xcffffffc.

Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
   CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
   (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
    created by PBL/configuration word within 0 - 3.5G memory range. The
    u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
   PBL/configuration word after switch to AS = 1
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: NKuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: NWood Scott-B07421 <B07421@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      7065b7d4
  35. 30 9月, 2011 3 次提交
    • K
      powerpc/85xx: Enable CMD_REGINFO on corenet boards · 9570cbda
      由 Kumar Gala 提交于 
      Useful for various debug to know how various regsters might be set
in a human readable form.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      9570cbda
    • A
      powerpc/85xx: Add FMan ethernet support to P4080DS · 2915609a
      由 Andy Fleming 提交于 
      Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.

The board supports add-on cards for SGMII and XAUI functionality.  Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.

Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register.  We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.

Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      2915609a
    • T
      powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros · e46fedfe
      由 Timur Tabi 提交于 
      Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.

CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file.  Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.

CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.

Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot).  All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      e46fedfe
  37. 29 7月, 2011 1 次提交
  39. 22 7月, 2011 1 次提交