-msingle-pic-base is a new gcc option for ppc and
it reduces the size of my u-boot with 6-8 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

-msingle-pic-base will be in gcc 4.6, however
backported patches are available at
http://bugs.gentoo.org/show_bug.cgi?id=347281Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>

The -fPIC flag belongs with -mrelocatable, move it there.
Also change -fPIC to -fpic as this produces smaller
binaries.
However, currently -mrelocatable promotes -fpic to -fPIC, a
fix for this is in upcoming gcc 4.6 or you can apply this small
patch to gcc:

diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 8da8410..e4b8280 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -227,7 +227,8 @@ do {									\
     }									\
 									\
   else if (TARGET_RELOCATABLE)						\
-    flag_pic = 2;							\
+    if (!flag_pic)							\
+      flag_pic = 2;							\
 } while (0)

 #ifndef RS6000_BI_ARCH
--
Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>

This patch fixes ea20 after 8ef583a0 where
the u-boot custom PHY_ macros were replaced with those of linux/mii.h MII_
definitions except in the RMII support for davinci_emac. Probably also due to
the merge path of changes in 2010.12.

Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: NMike Frysinger <vapier@gentoo.org>

This patch fixes ea20 after commit 6d8962e8
where $(obj)lib$(BOARD).a was changed to $(obj)lib$(BOARD).o in almost all the
Makefiles except ea20, probably due to merge path of the changes in 2010.12.

Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca>
CC: Sebastien Carlier <sebastien.carlier@gmail.com>
Acked-by : Stefano Babic <sbabic@denx.de>

For uImage always has a 64 bytes header, we couldn't expect to do
the xip from the header but should xip from the image start.

The latter logic in that section is also move the image from image_start
to the load address, so sync this logic to the xip operation.
Signed-off-by: NLei Wen <leiwen@marvell.com>
Acked-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

All of the spi flash drivers implement the status register polling for
detecting the device ready state, so unify them all in a new helper
function -- spi_flash_wait_ready.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These functions largely do the same exact thing, so unify them all
into one basic function.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Removed clearing of L2 cache as SRAM as it is not necessary without ECC.
This also speeds up the booting process.
Signed-off-by: NFabian Cenedese <cenedese@indel.ch>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:

9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPoonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.
Signed-off-by: NChunhe Lan <b25806@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NShaohui Xie <b21989@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Set default configuration to have SDHC controller enabled,
AUDIO enabled(codec clock sources is 12MHz) and disable TDM.
Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds
Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Make the support for ATI graphics cards mutually exclusive with DIU.
Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove the SERDES8 erratum work-around code that only applied to P4080
rev1, which is not supported by this version of U-Boot.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add documentation for the "serdes" hwconfig option, which is used to
specify the status of SerDes banks two and three for the SERDES8 erratum
work-around.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We don't really ever use Video cards on corenet_ds style boards and its
bloating our image which is close the its max size.  Drop support and
also kill some defines for non-PNP PCI which we never use.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Flash might be in unknown state when u-boot is started with jtag.
And got wrong env data. So reset it in board early init.

We cannot use generic cfi flash routines, because flash_init() is
not run yet.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>

renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.
Signed-off-by: NMatthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MAC address is stored in the last flash sector rather than OTP.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The MAC address is stored in the last flash sector rather than OTP.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

U-Boot itself takes up more than 0x40000 bytes, so we can't use that
sector for the environment.  Move it down a page.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The bfin_reset_or_hang function unnecessarily duplicates the panic()
logic based on CONFIG_PANIC_HANG.

This patch deletes 20 lines of code and just calls panic() instead.
This also makes the following generic-restart conversion patch simpler.
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Our monitor is always in RAM, so enable this define for the CFI layer.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Don't forget to count full data size for the multiblock operation request.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The timer register is 32bits, not 16bit, so 0xFFFF won't fill it.
Write out -1 to make sure to fill the whole thing.
Signed-off-by: NCliff Cai <cliff.cai@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Simple command to decode/check an LDR image before we try to boot it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Now that the common bootrom.h sets up defines for us, switch to them
rather than our own local set.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We need the updated LDR bit defines for our LDR utils.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This define isn't used anywhere anymore, so punt it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Some parts lack Bank B in L1 data, so have the linker script fall back to
Bank A when that happens.  This way we can still leverage L1 data.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

When bootstrapping ourselves on the fly at runtime (via "go"), we need to
turn off the caches to avoid taking software exceptions.  Since caches
need CPLBs and CPLBs need exception handlers, but we're about to rewrite
the code in memory where those exception handlers live, we need to turn
off caches first.

This new code also encourages a slight code optimization by storing the
MMR bases in dedicated registers so we don't have to fully load up the
pointer regs multiple times.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

If the part has no external memory configured, then there will be no os
log for us to check, and any attempt to access that memory will trigger
hardware errors.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>