- 31 5月, 2016 14 次提交
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由 Wills Wang 提交于
Add a platform prefix for function name in order to make more readable, and move it into ath79.h Signed-off-by: NWills Wang <wills.wang@live.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Daniel Schwierzeck 提交于
Add defconfigs for recently introduced MIPS64 support on Malta boards to get more build coverage for MIPS64. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Paul Burton 提交于
The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support. Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
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由 Paul Burton 提交于
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Paul Burton 提交于
Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
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由 Daniel Schwierzeck 提交于
Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Marek Vasut 提交于
Add ethernet driver for the AR933x and AR934x Atheros MIPS machines. The driver could be easily extended to other WiSoCs. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Wills Wang <wills.wang@live.com> [fixed Kconfig dependency] Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Add tune Kconfig option for MIPS 34kc. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Provide a default linker script for SPL binaries. Start address and size of text section and BSS section are configurable. All sections are arranged in a way that only relevant sections are kept in the code section for maximum size reduction. All other sections are kept but moved outside the code section to help with debugging. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Paul Burton 提交于
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards, which enables the user to make use of the whole 64 bit address space. Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
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由 Paul Burton 提交于
If dev->iobase is 64 bits wide then writing the value of the BAR into a pointer to iobase will not work on big endian systems, where the BAR value will incorrectly get written to the upper 32 bits of the 64 bit variable. Fix this by reading the BAR into a u32, matching the type expected by pci_read_config_dword. Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
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由 Paul Burton 提交于
Fix the pcnet driver to build safely on 64 bit platforms, in preparation for allowing MIPS64 builds for Malta boards. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Paul Burton 提交于
Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop manually converting addresses to their kseg0 equivalents in the pcnet driver. Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
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由 Paul Burton 提交于
Use CPHYSADDR to implement the virt_to_phys function for converting from a virtual to a physical address for MIPS32, much as is already done for MIPS64. This allows for virt_to_phys to work regardless of whether the address being translated is in kseg0 or kseg1, unlike the previous subtraction based approach which only worked for addresses in kseg0. This allows for drivers to provide an address to virt_to_phys without needing to manually ensure that kseg1 addresses are converted to equivalent kseg0 addresses first. This patch is equivalent to this Linux patch currently waiting to be reviewed & merged: https://patchwork.linux-mips.org/patch/12564/Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
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- 28 5月, 2016 26 次提交
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git://git.denx.de/u-boot-dm由 Tom Rini 提交于
For odroid-c2 (arch-meson) for now disable designware eth as meson now needs to do some harder GPIO work. Signed-off-by: NTom Rini <trini@konsulko.com> Conflicts: lib/efi_loader/efi_disk.c Modified: configs/odroid-c2_defconfig
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由 Lokesh Vutla 提交于
All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence. Reported-by: NRichard Woodruff <r-woodruff2@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NNishanth Menon <nm@ti.com>
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由 Robert P. J. Day 提交于
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
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由 Masahiro Yamada 提交于
Since f6c8f38e ("tools/genboardscfg.py: improve performance more with Kconfiglib"), this tool does not use the subprocess module. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Robert P. J. Day 提交于
In order for CONFIG_IS_ENABLED(FOO) to work we need to move the changes that CONFIG_FIT_DISABLE_SHA256 makes to be prior to the evaluation by CONFIG_IS_ENABLED(foo) Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca> [trini: Move CONFIG_FIT_DISABLE_SHA256 parts to fix build breakage] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Masahiro Yamada 提交于
Since 1e6ad55c ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
We should say "clean & invalidate", or simply "flush". Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
__asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Lokesh Vutla 提交于
Different AM335x based platforms have different serial consoles. As serial console is Kconfig option a separate defconfig has to be created for each platform. So pass the serial device dynamically. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add minimal dts support for AM335x-ICEv2 board Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
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由 Lokesh Vutla 提交于
Populate the right dtb file and console for AM335x-ICEv2 board. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
In order to enable cpsw on AM335x ICEv2 board, the following needs to be done: 1)There are few on board jumper settings which gives a choice between cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting this, there are few GPIOs which control these muxes that needs to be held high. 2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected via I2C. This needs to properly programmed and locked for PHY operation. And PHY needs to be reset before before being used, which is also held by a GPIO. 3) RMII mode needs to be selected. [1] http://www.ti.com/lit/zip/tidr336 [2] http://www.ti.com/lit/ds/symlink/cdce913.pdfReviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NMugunthan V N <mugunthanvnm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
The CDCE913 and CDCEL913 devices are modular PLL-based, low cost, high performance , programmable clock synthesizers. They generate upto 3 output clocks from a single input frequency. Each output can be programmed for any clock-frequency. Adding support for the same. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125), capable of running at 400MHz. Adding this specific DDR configuration details running at 400MHz. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add necessary pinmux support for AM335x ICEv2 board. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Similar to other TI's AM335x platforms, AM335x ICEv2 also has an eeprom populated for its unique identification. Adding this info so that AM335x ICEv2 specific initialization can be done. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Tom Rini 提交于
Re-org env sections so that we can fall back to env is in FAT on SD card, for broader board compatibility Signed-off-by: NTom Rini <trini@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add initial DTS support for AM335x-BBG Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add initial DTS support for AM335x-evm sk. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Mugunthan V N 提交于
As per mmc device tree binding documentation card detect gpio has to be active low signal. When a hardware is designed with active high card detect, gpio polarity has to be changed with cd-inverted dt property. In AM335x the card detect gpio is designed as active low gpio. So correcting the dt card detect gpio definition. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Lokesh Vutla 提交于
Use a single defconfig for all AM335x platforms by enabling FIT Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Allow am335x-bone.dts to be built and enable uart and timer for all beaglebones. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
FIT allows for a multiple dtb in a single image. SPL needs a way to detect the right dtb to be used. Adding support for the same. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Convert usb host boot defconfig to use DM, DT. Also enable FIT support. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add initial DTS support for AM437x-IDK evm. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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