1. 31 1月, 2016 3 次提交
    • A
      armv7: add cacheline sizes where missing · 3709844f
      Albert ARIBAUD 提交于
      Some armv7 targets are missing a cache line size declaration.
      In preparation for "arm: cache: Implement cache range check for v7"
      patch, add these declarations with the appropriate value for
      the target's SoC or CPU.
      Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
      Reviewed-by: NTom Rini <trini@konsulko.com>
      3709844f
    • M
      arm: Remove S bit from MMU section entry · 8890c2fb
      Marek Vasut 提交于
      Restore the old behavior of the MMU section entries configuration,
      which is without the S-bit.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@konsulko.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Simon Glass <sjg@chromium.org>
      8890c2fb
    • M
      arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 · a592e6fb
      Marek Vasut 提交于
      The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
      set, it configures TTBR0 register. This register must be configured for the
      cache on ARMv7 to operate correctly.
      
      The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
      TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
      issues which are hard to replicate, for example certain USB sticks are not
      detected or QSPI NOR sometimes fails to write pages completely.
      
      The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
      correct because the code which added the test(s) for CONFIG_ARMV7 was added
      shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
      not adjusted correctly to reflect that change.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@konsulko.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Simon Glass <sjg@chromium.org>
      a592e6fb
  2. 30 1月, 2016 20 次提交
  3. 29 1月, 2016 17 次提交