- 28 12月, 2007 11 次提交
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由 Stefan Roese 提交于
Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Now that the 440EPx ECC test is not board specific anymore remove this Makefile. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Anatolij Gustschin 提交于
ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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由 Niklaus Giger 提交于
Signed-off-by: NNiklaus Giger <niklaus.giger@netstal.com>
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由 Markus Klotzbücher 提交于
When using dhcp/bootp the "netmask" environment variable is not set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is desireable, so the following patch adds this this option to the board config. Signed-off-by: NMarkus Klotzbuecher <mk@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Larry Johnson 提交于
This patch allows the ECC POST to be used for different boards with the PPC440 Denali SDRAM controller. Modifications include skipping the test if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization to prevent timing errors. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Matthias Fuchs 提交于
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Matthias Fuchs 提交于
flush + invalidate_dcache_range() expect the start and stop+1 address. So the stop address is the first address behind (!) the range. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Stefan Roese 提交于
By using aliases in the dts file, the ethernet node fixup is much easier with the recently added functions. Please note that the dts file needs the aliases for this to work. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: NStefan Roese <sr@denx.de>
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- 11 12月, 2007 3 次提交
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由 Stefan Roese 提交于
Thanks to Gary Jennejohn for pointing this out. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Conflicts: drivers/rtc/Makefile
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- 08 12月, 2007 1 次提交
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由 Stefan Roese 提交于
This patch selects the USB data pins in the 405EX GPIO and MFC (multi function control) registers. This is done for the AMCC Kilauea and Makalu eval boards. Signed-off-by: NStefan Roese <sr@denx.de>
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- 06 12月, 2007 3 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Stefan Roese 提交于
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by setting the FIXD bit in the SDR0_MFR register. Here a description of the symptoms: Problem Description ------------------------------ If a DMA is performed between memory and PCI with the DMA 1 Controller using prefetch, and as a result uses a special purpose buffer selected by the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), the first part of the transfer sequence is performed twice. The PPC440SPe PCI Controller requests more data than was needed such that in the case of enforce memory protection, a host CPU exception can occur. No data is corrupted, because data transfer is stopped in the PCI Controller. Prefetch enable is specified by setting DMA Configuration Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. Behavior that may be observed in a running system --------------------------------------------------------------------------- 1. DMA performance is decreased because of the double access on the PCI bus interface. 2. If an illegal access to some address on the PCI bus is detected at the system level, a machine check or similar system error may occur. Workarounds Available ---------------------------------- 1. Do not program prefetch. Note that a prefetch command cannot be programmed without selecting a special purpose buffer. 2. To avoid crossing a physical boundary of the PCI slave device, add 512 bytes of address to the PCI address range. This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com> from AMCC and slighly changed. Signed-off-by: NPravin M. Bathija <pbathija@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 04 12月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 03 12月, 2007 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 30 11月, 2007 1 次提交
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由 Stefan Roese 提交于
This manual PCIe reset triggering solves the problem seen with the Intel EPRO/1000 card, which was not detected (link not established) upon power-up reset. Signed-off-by: NStefan Roese <sr@denx.de>
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- 27 11月, 2007 6 次提交
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由 Stefan Roese 提交于
After an error in the AMCC 405EX users manual now correctly configure IRQ2 (Kilauea)/IRQ0 (Makalu) as alternate 2 signal for external IRQ usage. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
Conflicts: Makefile Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 26 11月, 2007 13 次提交
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由 Stefan Roese 提交于
As suggested by Senao, use a different EBC_PB0AP setup for 400MHz operation. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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