Add support of SerDes framework for Layerscape Architecture.
    - Add support of 2 SerDes block
    - Add SerDes protocol parsing and detection
    - Create table of SerDes protocol supported by LS2085A
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.

Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.

Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.

Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.

Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Npankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: NRoy Pledge <Roy.Pledge@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

The serial nodes in the fsl-lsch3 device trees have compatible =
"fsl,ns16550", "ns16550a" -- so don't look for "ns16550".
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Without this "USB may not work" according to the erratum text, though I
did not notice a problem without it.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.

Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.
Signed-off-by: NYork Sun <yorksun@freescale.com>

This is required for TLB invalidation broadcasts to work.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add support for reset_cpu() by asserting RESET_REQ_B.
Signed-off-by: Npankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>

Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.
Signed-off-by: NYork Sun <yorksun@freescale.com>

ls2085a_common.h contains hard-coded information for NOR/NAND flash,
I2C, DDR, etc. These are platform specific. Move them out of common
header file and placed into respective board header files.

Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector
size.

Enable command auto complete. Update prompt symbol. Set fdt_high to
0xa0000000 because Linux requires that the fdt  be 8-byte aligned
and below 512 MiB. Besides ensuring compliance with the 512 MiB
limit, this avoids problems with the dtb being misaligned within
the FIT image.

Change the MC FW, MC DPL and Debug server NOR addresses in compliance
with the NOR flash layouts for 128MB flash.

Add PCIe macros. Enable "loadb" command. Disable debug server.
Enable workaround for erratum A008511.
Stop reset on panic for postmortem debugging.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.
Signed-off-by: NYork Sun <yorksun@freescale.com>

The patch removes unnecessary whitespace to fix checkpatch's
warning: unnecessary whitespace before a quoted newline
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Otherwise the high 32 bits get truncated on 64-bit U-boot.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.
Signed-off-by: NYork Sun <yorksun@freescale.com>

CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Some SoCs have more than two I2C busses. Instead of adding ifdef
to the driver, macros are put into board header file where
CONFIG_SYS_I2C_MXC is defined.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>

IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers.  Fix the resulting array overflow.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Increase malloc length for more than 2M.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LDPAA Ethernet driver is a freescale's new ethernet driver based on
Layerscape architecture.

Every ethernet driver controls on DPNI object. Where all DPNIs share
one common DPBP and DPIO object to support  Rx and Tx flows.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
CC: Cristian Sovaiala <cristian.sovaiala@freescale.com>
CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
CC: J. German Rivera <German.Rivera@freescale.com>
[York Sun: s/NetReceive/net_process_received_packet]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Freescale's Layerscape Management Complex (MC) provide support various
objects like DPRC, DPNI, DPBP and DPIO.
Where:
	DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO
	DPBP: Management of buffer pool
	DPIO: Used for used to QBMan portal
	DPNI: Represents standard network interface

These objects are used for DPAA ethernet drivers.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NGeoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NCristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: Npankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds description for NOR flash layout (firmware images)
in the README file for LS2085A platforms.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:

MC DDR region start = Top of DDR - area reserved by Debug Server FW
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Check if USB Erratum A005697 is applicable on BSC913x and
add corresponding  property in the device tree via device
tree fixup which is used by linux driver
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
   to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
   has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
   must set this bit before change DBI register value.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add following affected SOCs and their personalities for USB
Erratum A007792 :
        T1040 Rev 1.1
        T1024 Rev 1.0
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode
for all these socs. This is required for supporting deel-sleep feature
in linux for usb driver
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

1. Default environment will be used for secure boot flow
 which can't be edited or saved.
2. Command for secure boot is predefined in the default
 environment which will run on autoboot (and autoboot is
 the only option allowed in case of secure boot) and it
 looks like this:
 #define CONFIG_SECBOOT \
 "setenv bs_hdraddr 0xe8e00000;"                 \
 "esbc_validate $bs_hdraddr;"                    \
 "source $img_addr;"                             \
 "esbc_halt;"
 #endif
3. Boot Script can contain esbc_validate commands and bootm command.
 Uboot source command used in default secure boot command will
 run the bootscript.
4. Command esbc_halt added to ensure either bootm executes
 after validation of images or core should just spin.
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: NGaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

On QDS board with DDR4 DIMM, LPUART is used as console
output to verify DCU driver. This patch adds
ls1021aqds_ddr4_nor_lpuart_defconfig for this support.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Freescale LS1021ATWR share some pins. Hwconfig option is used to
allows users to choose the pin functions.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
[York Sun: revised commit message]
Reviewed-by: NYork Sun <yorksun@freescale.com>

For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

commit aed2fbef
"dm: serial: Tidy up the pl01x driver"
caused a regression on (real hardware) PL010 by omitting
to update the line control register when switching baudrate.

Fix this by inlining the missing write to the baud control
register.

Also renaming the set_line_control() function to
pl011_set_line_control() since this function is clearly
PL011-specific, and it won't suffice to call that to
set up line control.

Tested on the Integrator/AP hardware.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

two CMD_DNS options were added by commit 60296a83 ("commands: add more
command entries in Kconfig")
Signed-off-by: NAndrey Skvortsov <andrej.skvortzov@gmail.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>