- "env ask", "env grep" and "setexpr" are needed for commissioning
- add support for ext4 file systems
- adjust default environment to use ext4 commands
- add write support for (V)FAT and EXT4
- add bitmap and splashscreen support
- print timestamp information for images
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

With CONFIG_SYS_GENERIC_BOARD the board hangs after issuing a 'save' command.

Remove CONFIG_SYS_GENERIC_BOARD until this issue can be fixed properly.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

commit 67a04ab3
fix the build for MX25. The same error
happens for VF610 SOC.
Signed-off-by: NStefano Babic <sbabic@denx.de>

According to:

http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0

ENGR00287268 mx6: fix the secure boot issue on the new tapout chip
commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b

newer i.MX6 silicon revisions have an updated ROM and HAB API table.
Please see also:

i.MX Applications Processors Documentation
Engineering Bulletins
EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison

With this change the secure boot status is correctly displayed
Signed-off-by: NStefano Babic <sbabic@denx.de>

Explain the necessary steps in order to boot from SPI NOR.

Based on a earlier submission from Mårten Wikman.
Signed-off-by: NMårten Wikman <marten.wikman@novia.fi>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Introduce 'mx28evk_spi' target which will store the environment variables
into SPI NOR, which is useful when booting from SPI NOR.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

When building a target with CONFIG_ENV_IS_IN_SPI_FLASH the following
warning is seen:

include/configs/mx28evk.h:73:0: warning: "CONFIG_ENV_SIZE" redefined [enabled by default]

Protect the definition of CONFIG_ENV_SIZE to avoid the warning.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The name of the dtb file used in the kernel is 'imx6dl-riotboard.dtb', so fix
it accordingly.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Tested-by: NIain Paton <ipaton0@gmail.com>

mars and riot boards use UART2 as console, so CONFIG_CONSOLE_DEV should point
to 'ttymxc1' instead.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Tested-by: NIain Paton <ipaton0@gmail.com>

Commit e9fd66de (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables
errata 742230 for imx6, because it helps remove one reboot issue.
However, this errata does not really apply on imx6, because Cortex-A9
on imx6 is r2p10 while the errata only applies to revisions r1p0..r2p2.

At a later time, commit f71cbfe3 (ARM: Add workaround for Cortex-A9
errata 794072) adds support of errata 794072, which applies to all
Cortex-A9 revisions.  As the workaround for both errata are exactly
same, it makes a lot more sense to select 794072 instead of 742230 for
imx6.  Since we already enable 794072 for imx6, it's time to drop
errata 742230 to avoid confusion.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Acked-by: NNitin Garg <nitin.garg@freescale.com>

Signed-off-by: NMarek Vasut <marex@denx.de>

mx6 reference manual incorrectly states that the DEVICE_TYPE field of
IOMUXC_GPR12 register should be configured as '0010' for setting the PCI
controller in RC mode. The correct value should be '0100' instead.

This also aligns with the same value used in the mx6 pci kernel driver.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NStefano Babic <sbabic@denx.de>

THe mx25 arch does not have a sys_proto.h file.
Instead of creating a dummy file, the file
is not included for this SOC.
Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return
instead of configuring the SATA clock and GPR13 registers.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure
instead of attempting a memory access that results in a data abort and reset.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Switch to an SPL image. The SPL for Ventana does the following:
 - setup i2c and read the factory programmed EEPROM to obtain DRAM config
   and model for board-specific calibration data
 - configure DRAM per CPU/size/layout/devices/calibration
 - load u-boot.img from NAND and jump to it

This allows for a single SPL+u-boot.img to replace the previous multiple boa
configurations.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

use the new iomux function and a macros to create a multi-dimensional array
of iomux values without duplicating the defintions.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Split the read_eeprom function out so that it can be shared (ie with SPL)

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
  chip-specific data

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Add memory-mapped structures for MMDC iomux and configuration. Note that whi
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
registers differ. This requires two sets of structures.

Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration registers that can be used to
configure the MMDC dynamically.

We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Acked-by: NNikita Kiryanov <nikita@compulab.co.il>

Add comment block for the imx_ddr_size function and remove the extra unused
fields from struct esd_mmdc_regs which are also not common between IMX53 and
IMX6.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Acked-by: NNikita Kiryanov <nikita@compulab.co.il>

Add a common spl.c file to support boot device functions needed for SPL
such as detecting the boot device.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Acked-by: NNikita Kiryanov <nikita@compulab.co.il>

Add a common header which can hopefully be shared amon imx6 SPL users

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Acked-by: NNikita Kiryanov <nikita@compulab.co.il>

This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.

But many of them just define BOOT_DEVICE_* macros.

Those macros are used in the "switch (boot_device) { ... }"
statement in common/spl/spl.c.

So they should not be archtecture specific, but be described as
a simpile enumeration.

This commit merges most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.

With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Acked-by: NMichal Simek <monstr@monstr.eu>
Acked-by: NStefano Babic <sbabic@denx.de>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NTim Harvey <tharvey@gateworks.com>
Tested-by: Bo Shen <voice.shen@atmel.com> [on sama5d3xek board for at91 part]
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: Stefano Babic <sbabic@denx.de> [applying Tim's i.MX6 patches]
Acked-by: NTom Rini <trini@ti.com>

Bit 7 of UCR3 is described in the i.MX3x/i.MX5x/i.MX6x
reference manuals as follows:

	Autobaud Detection Not Improved-. Disables new features of
	autobaud detection (See Baud Rate Automatic Detection
        Protocol, for more details).

	0 Autobaud detection new features selected
	1 Keep old autobaud detection mechanism

On at least i.MX6DQ, i.MX6DLS and i.MX53, the "new features"
occasionally cause the receiver to get out of sync and
continuously produce received characters of '\xff'.

This patch disables the "new feature" on all boards, since
there's no support for auto-baud in U-Boot on any of them.

More details are available in this post on i.MX Community:
	https://community.freescale.com/message/403254Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>

mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus.

Add support for it
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Tested by booting a mainline kernel via TFTP.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The correct value for this setting can vary across SoCs and boards, so make it
configurable.

Also reduce the default value to 8, which is the same default as used in the
Linux driver.
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>

On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
> The {r,t}xbuffs fields also need to be aligned. Previously this was done
> implicitly because they immediately followed the descriptor tables. Make this
> explicit and also move to the head of the struct.

Looks like I managed to not actually commit the move of the field to the
head of the struct! v3.1 follows....

Ian.

8<------------

>From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Thu, 1 May 2014 19:45:15 +0100
Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
 efficiently.

The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.

Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.

The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Tested-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>

This is required at least on ARM.

When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>

struct dw_eth_dev contains fields which are accessed via DMA, so make sure it
is aligned to a dma boundary. Without this I see:
    ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NAlexey Brodkin <abrodkin@synopsys.com>
Acked-by: NMarek Vasut <marex@denx.de>

Add support for booting from an MMC card.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NHenrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NMarek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: NTom Rini <trini@ti.com>

On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > +	case 1:
> > +#if CONFIG_MMC1_PG

> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?

It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...

> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.

...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.

> Other than this please add my:
>
> Reviewed-by: Stefan Roese <sr@denx.de>

Thanks!

8<---------------------------------

>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support

This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.
Signed-off-by: NHenrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: NLuke Leighton <lkcl@lkcl.net>
Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NWills Wang <wills.wang.open@gmail.com>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NStefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Cc: Aaron Maoye <leafy.myeh@allwinnertech.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: NTom Rini <trini@ti.com>

Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i)
processors. Enable for the Cubietruck.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NJens Kuske <jenskuske@gmail.com>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NTom Rini <trini@ti.com>

Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NJens Kuske <jenskuske@gmail.com>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NTom Rini <trini@ti.com>
Reviewed-by: NMarek Vasut <marex@denx.de>

This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.
Signed-off-by: NAdam Sampson <ats@offog.org>
Signed-off-by: NAleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHenrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: NJens Kuske <jenskuske@gmail.com>
Signed-off-by: NLuc Verhaegen <libv@skynet.be>
Signed-off-by: NLuke Leighton <lkcl@lkcl.net>
Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NPatrick Wood <patrickhwood@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NWills Wang <wills.wang.open@gmail.com>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NMarek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: NTom Rini <trini@ti.com>

This patch adds DRAM initialisation support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.
Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHenrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: NJens Kuske <jenskuske@gmail.com>
Signed-off-by: NLuke Leighton <lkcl@lkcl.net>
Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Reviewed-by: NMarek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: NTom Rini <trini@ti.com>