- 29 3月, 2017 40 次提交
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由 Stefan Roese 提交于
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Read the "phy-speed" DT property to differentiate between 1 and 2.5GB SGMII operations. Please note that its unclear right now, if this DT property will be accepted in mainline Linux. If not, we need to revisit this code and change it to use the accepted property. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch does a bit of restructuring of the probe / init functions, mainly to allow earlier register access as it is needed for the upcoming GoP (Group of Ports) and NetC (Net Complex) code. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds the PPv2.2 specific FIFO configuration to the mvpp2 driver. The RX FIFO packet data size is changed to the recommended FIFO sizes. The TX FIFO configuration is newly added. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Currently, the naming of the ethernet ports is not handled correctly in the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP also instantiates an ethernet controller with the same device ID's. This patch now takes this into account and adds the required base-id so that the slave-CP ethernet devices will be named "mvpp2-3 ...". This patch also updates my Copyright notice to include 2017 as well. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Since we've now integrated the A7k/8k support in the mvpp2 ethernet driver, lets enable the support for both Marvell developments boards. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit adds the description of the PPv2.2 hardware block for the Marvell Armada 7K and Armada 8K processors, and their corresponding Armada 7040 and 8040 Development boards. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Since Armada 7K/8K is also equipped with a newer version of the MVPP2 ethernet controller, lets enable compilation of this driver for these platforms. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This fixes problems noticed with the PPv2.2 A7k/8k port, when not all elements of the descriptors had been cleared before use. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch moves the base_probe function mvpp2_base_probe() from the MISC driver to the ETH driver. When integrated in the MISC driver, probe is called too early before the U-Boot ethernet infrastructure (especially the MDIO / PHY interface) has been initialized. Resulting in errors in mdio_register(). Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver, currently only supporting the 32bit platforms (Armada 37x). This patch now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF can be used as well on these platforms. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Now that the mvpp2 driver has been modified to accommodate the support for PPv2.2, we can finally advertise this support by adding the appropriate compatible string. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4 RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7 to the second port, 8->11 to the third port, etc. In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate RXQs from the range of 32 RXQs available for each port. So port 0 must use RXQs in the range 0->31, port 1 in the range 32->63, etc. This commit adapts the mvpp2 to this difference between PPv2.1 and PPv2.2: - The constant definition MVPP2_MAX_RXQ is replaced by a new field 'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of RXQs per port. This field is initialized during ->probe() depending on the IP version. - MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total number of RXQs by multiplying the number of ports by the maximum of RXQs per port. This was anyway used in only one place. - In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted to cope with the different allocation strategy between PPv2.1 and PPv2.2. Due to this change, the 'next_first_rxq' argument of this function is no longer needed and is removed. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is configured, since it changed between PPv2.1 and PPv2.2. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this commit adds the necessary initialization of the AXI bridge. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit handles a few miscellaneous differences between PPv2.1 and PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY polling, etc.). Changed by Stefan for U-Boot: Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot version of this patch does not remove this function but simply adds the check for MVPP21 before the mvpp2_port_fc_adv_enable() call. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit adjusts the mvpp2 driver register mapping and access logic to support PPv2.2, to handle a number of differences. Due to how the registers are laid out in memory, the Device Tree binding for the "reg" property is different: - On PPv2.1, we had a first area for the common registers, and then one area per port. - On PPv2.2, we have a first area for the common registers, and a second area for all the per-ports registers. In addition, on PPv2.2, the area for the common registers is split into so-called "address spaces" of 64 KB each. They allow to access the same registers, but from different CPUs. Hence the introduction of cpu_base[] in 'struct mvpp2', and the modification of the mvpp2_write() and mvpp2_read() register accessors. For PPv2.1, the compatibility is preserved by using an "address space" size of 0. Changed by Stefan for U-Boot: Since we don't support multiple CPUs in U-Boot, I've removed all the code, macros and variables introduced in the Linux patch version for this. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG registers have a slightly different layout, because they need to contain a 64-bit address for the RX and TX descriptor arrays. This commit adjusts those functions accordingly. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit modifies the mvpp2_defaults_set() function to not do the loopback and FIFO threshold initialization, which are not needed for PPv2.2. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The MVPP2_RXQ_CONFIG_REG register has a slightly different layout between PPv2.1 and PPv2.2, so this commit adapts the functions modifying this register to accommodate for both the PPv2.1 and PPv2.2 cases. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit adjusts the allocation and freeing of BM pools to support PPv2.2. This involves: - Checking that the number of buffer pointers is a multiple of 16, as required by the hardware. - Adjusting the size of the DMA coherent area allocated for buffer pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per buffer, as opposed to 2 pointers of 32-bits per buffer in PPv2.1. The size in bytes is now stored in a new field of the mvpp2_bm_pool structure. - On PPv2.2, getting the physical and virtual address of each buffer requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order bits of those addresses. A new utility function mvpp2_bm_bufs_get_addrs() is introduced to handle this. - On PPv2.2, releasing a buffer requires writing the high order 32 bits of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
This commit adds the definition of the PPv2.2 HW descriptors, adjusts the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts the accessors to work on both PPv2.1 and PPv2.2. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Since the format of the HW descriptors is different between PPv2.1 and PPv2.2, this commit introduces an intermediate union, with for now only the PPv2.1 descriptors. The bulk of the driver code only manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the descriptors can only be accessed and modified through the accessor functions. A follow-up commit will add the descriptor definitions for PPv2.2. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
In preparation to the introduction for the support of PPv2.2 in the mvpp2 driver, this commit adds a hw_version field to the struct mvpp2, and uses the .data field of the DT match table to fill it in. Having the MVPP21 and MVPP22 definitions available will allow to start adding the necessary conditional code to support PPv2.2. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The PPv2.2 IP has a different TX and RX descriptor layout compared to PPv2.1. In order to prepare for the introduction of PPv2.2 support in mvpp2, this commit adds accessors for the different fields of the TX and RX descriptors, and changes the code to use them. For now, the mvpp2_port argument passed to the accessors is not used, but it will be used in follow-up to update the descriptor according to the version of the IP being used. Apart from the mechanical changes to use the newly introduced accessors, a few other changes, needed to use the accessors, are made: - The mvpp2_txq_inc_put() function now takes a mvpp2_port as first argument, as it is needed to use the accessors. - Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first argument, for the same reason. - In mvpp2_rx_error(), instead of accessing the RX descriptor in each case of the switch, we introduce a local variable to store the packet size. - Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie" variable to store the RX descriptor cookie, rather than accessing it from the descriptor each time. - In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the packet size from the TX descriptor, we use the actual value available in the function, which is used to set the TX descriptor packet size a few lines before. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
As indicated by Russell King, the mvpp2 driver currently uses a lot "phys" or "phys_addr" to store what really is a DMA address. This commit clarifies this by using "dma" or "dma_addr" where appropriate. This is especially important as we are going to introduce more changes where the distinction between physical address and DMA address will be key. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Some more U-Boot specific 64bit support changes, mostly changing u32 to unsigned long. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The mvpp2 is going to be extended to support the Marvell Armada 7K/8K platform, which is ARM64. As a preparation to this work, this commit enables building the mvpp2 driver on ARM64, by: - Adjusting the Kconfig dependency - Fixing the types used in the driver so that they are 32/64-bits compliant. We use dma_addr_t for DMA addresses, and unsigned long for virtual addresses. It is worth mentioning that after this commit, the driver is for now still only used on 32-bits platforms, and will only work on 32-bits platforms. Changed by Stefan for U-Boot: Removed the Kconfig change as it does not apply to U-Boot this way. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which doesn't compile nicely on 64-bit. Moreover, those definitions are in fact unneeded, since they are always used in combination with a bit mask that ensures only the appropriate bits are modified. Therefore, such definitions should just be set to 0x0. In addition, as suggested by Russell King, we change the _MASK definitions to also use the BIT() macro so that it is clear they are related to the values defined afterwards. For example: #define MVPP2_PRS_RI_L2_CAST_MASK 0x600 #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) becomes #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) #define MVPP2_PRS_RI_L2_UCAST 0x0 #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and MVPP2_PRS_RI_L2_BCAST) are always applied with MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)). It fixes the following warnings when building the driver on a 64-bit platform (which is not possible as of this commit, but will be enabled in a follow-up commit): drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’: drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow] #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) ^ drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The mvpp2_bm_bufs_add() currently creates a fake cookie by calling mvpp2_bm_cookie_pool_set(), just to be able to call mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID. Instead of doing this convoluted thing, just call mvpp2_bm_pool_put() directly, since we have the BM pool ID. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail. This gets rid of the warnings: CACHE: Misaligned operation at range ... Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is defined in the bitsperlong.h header. Lets include this header as the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver uses this macro. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Vlad Zakharov 提交于
This commit replaces legacy timer code with usage of arc timer driver. It removes arch/arc/lib/time.c file and selects CONFIG_CLK, CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default. Therefore we remove CONFIG_CLK option from less common axs101 and axs103 defconfigs. Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from axs10x.h, tb100.h and nsim.h configs files as it is no longer required. Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Vlad Zakharov 提交于
We want to use the same device tree blobs in both Linux and U-Boot for ARC boards. Earlier device tree sources in U-Boot were very simplified and hadn't been updated for quite a long period of time. So this commit is the first step on the road to unified device tree blobs. First of all we re-organize device tree sources for AXS10X boards. As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and AXC003 cpu tiles respectively we add corresponding device tree source files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for cpu tiles and axs101.dts and axs103.dts to represent actual boards. Also we delete axs10x.dts as it is no longer used. One more important change - we add timer device to ARC skeleton device tree sources as both ARC700 and ARCHS cores contain such timer. We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree sources as it is referenced via phandle from timer node in common skeleton.dtsi file. Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Vlad Zakharov 提交于
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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