- 10 10月, 2014 1 次提交
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由 Roger Quadros 提交于
On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: NRoger Quadros <rogerq@ti.com>
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- 08 10月, 2014 1 次提交
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由 Hans de Goede 提交于
In order for the gmac nic to work reliable on the Bananapi, we need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register (0x01c20164) to 3. Without this about 9 out of 10 ethernet packets get lost, with this setting there is no packet loss. So far setting these bits is only necessary on the Bananapi, so this commit solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we need to do something similar for other boards, we can create a specific CONFIG_FOO option for this then. Reported-by: NKarsten Merker <merker@debian.org> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Tested-by: NKarsten Merker <merker@debian.org> Tested-by: NZoltan HERPAI <wigyori@openwrt.org> Tested-by: NTony Zhang <tony.zhang@lemaker.org> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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- 07 10月, 2014 1 次提交
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由 Anthony Felice 提交于
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: NAnthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: NStefan Agner <stefan@agner.ch>
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- 06 10月, 2014 5 次提交
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由 Marek Vasut 提交于
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Cosmetic change to the checkboard() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NPavel Machek <pavel@denx.de>
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由 Pavel Machek 提交于
The bi_boot_params must point to offset 0x100 in DRAM. Make it so. Signed-off-by: NPavel Machek <pavel@denx.de> Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
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由 Marek Vasut 提交于
Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com> Acked-by: NPavel Machek <pavel@denx.de>
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- 26 9月, 2014 1 次提交
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由 York Sun 提交于
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
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- 25 9月, 2014 11 次提交
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由 York Sun 提交于
Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 York Sun 提交于
DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Masahiro Yamada 提交于
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Since commit ddaf5c8f (patman: RunPipe() should not pipe stdout/stderr unless asked), Patman spits lots of "Invalid MAINTAINERS address: '-'" error messages for patches with global changes. It takes too long for Patman to process them. Anyway, "M: -" does not carry any important information. Rather, it is just like a place holder in case of assigning a new board maintainer. Let's comment out. This commit can be reproduced by the following command: find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/' Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
The "S: Orphan" in MAINTAINERS means that the maintainer in the "M:" field is unreachable (i.e. the email address is not working). (Refer to the definition of "Orphan" adopted in U-Boot in the log of commit 31f1b654, "boards.cfg: move boards with invalid emails to Orphan") For patch files adding global changes, scripts/get_maintainer.pl adds bunch of such invalid email addresses, which results in tons of annoying bounce emails. This commit can be reproduced by the following command: find . -name MAINTAINERS | xargs sed -i -e ' /^M:[[:blank:]]/ { N /S:[[:blank:]]Orphan/s/^/#/ } ' Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
Each CPU of PowerPC has its default linker script under the CPU directory, except mpc8xx. Every mpc8xx board has its own linker script under the board directory, resulting in lots of duplication of linker scripts. I notice eight mpc8xx boards have the same linker script. We can decrease the number of linker scripts by putting a single default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: NStefan Roese <sr@denx.de>
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由 Priyanka Jain 提交于
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
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由 Priyanka Jain 提交于
DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 vijay rai 提交于
T1042RDB is a Freescale reference board that hosts the T1042 SoC (and variants). The board is similar to T1040RDB, T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). T1042RDB is configured with serdes protocol 0x86 which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 DTSEC1, DTSEC2 are not connected on board. This Patch - add T1042RDB support - updates README file for T1042RDB details and update commands for switching to alternate banks from vBank0 to vBank4 and vice versa This patch also does minor clean ups for fdt defines for T1042RDB and T1042RDB_PI board Signed-off-by: NVijay Rai <vijay.rai@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 vijay rai 提交于
This patch adds support of rcw for T1042RDB, it makes following changes : - Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB - Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates comments for valid serdes protocol which is 0x06 - Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB Signed-off-by: NVijay Rai <vijay.rai@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 24 9月, 2014 1 次提交
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由 Nikita Kiryanov 提交于
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value: cs = (cs | gpio << 8) This merge of cs and gpio data into one value breaks the sf probe command: if the use of gpio is required, invoking "sf probe <cs>" will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must type "sf probe 15872". This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details. Fix this by introducing a new board function: board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary. Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Eric Benard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: NMarek Vasut <marex@denx.de> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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- 22 9月, 2014 1 次提交
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- Use _defconfig instead of _config, but still _config is working. - Corrected README.sandbox path in ./README Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 19 9月, 2014 1 次提交
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由 Bo Shen 提交于
Add NOR flash hardware init function, including SMC and PIO configuration. Signed-off-by: NBo Shen <voice.shen@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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- 18 9月, 2014 1 次提交
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由 Murali Karicheri 提交于
This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NKeegan Garcia <kgarcia@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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- 17 9月, 2014 2 次提交
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: NSteve Rae <srae@broadcom.com> Cc: David Feng <fenghua@phytium.com.cn>
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- 14 9月, 2014 1 次提交
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由 Masahiro Yamada 提交于
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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- 11 9月, 2014 1 次提交
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由 Simon Glass 提交于
This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 09 9月, 2014 12 次提交
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由 Fabio Estevam 提交于
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board. Provide a DCD configuration file specific to mx6dlsabresd with the settings recommended by the Freescale hardware team. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Thierry Reding 提交于
The leds array within struct ventana has space for 3 elements, but the setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent versions of GCC complain about that: board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio': board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations] if (gpio_cfg[board].leds[i]) ^ board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop for (i = 0; i < 4; i++) { ^ Fix this by making the upper bound of the loop match the array size. Signed-off-by: NThierry Reding <treding@nvidia.com> Acked-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion. These boards use GPIO on the PLX device as PERST# for the downstream ports thus we assert this when the PLX is enumerated. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Nikita Kiryanov 提交于
Add support for SATA. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Use Compulab eeprom module to obtain revision number, serial number, and mac address from the EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add support for all 3 I2C busses on Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add USB and USB OTG host support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add ethernet support for Compulab CM-FX6 CoM Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add NAND support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Acked-by: NIgor Grinberg <grinberg@compulab.co.il> Acked-by: NDmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: NMarek Vasut <marex@denx.de> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Tim Harvey 提交于
There are many similarities between the IMX6QUAD/IMX6DUAL and there are many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env variable that tells you which type you have. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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