- 19 2月, 2018 15 次提交
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由 Jean-Jacques Hiblot 提交于
When the clock is applied, compute the actual value of the clock. It may be slightly different from the requested value (max freq, divisor threshold) Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
The default configuration is usually working fine for the the HS modes. Don't enforce the presence of a dedicated pinmux for the HS modes. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
AM572x SR1.1 requires different IODelay values to be used than that used in AM572x SR2.0. These values are populated in device tree. Add capability in omap_hsmmc driver to extract IOdelay values for different silicon revision. The maximum frequency is also reduced when using a ES1.1. To keep the ability to boot both revsions with the same dtb, those values can be provided by the platform code. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to parse mux values and iodelay values from device tree and set these depending on the enumerated MMC mode. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
Add a new API to perform iodelay recalibration without isolate io to be used in uboot. The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. The MMC driver can use the new API to set the IO delay values depending on the MMC mode. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
Use the mmc_of_parse library function to populate mmc_config instead of repeating the same code in host controller driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
>From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines reset procedure section in TRM suggests to first poll the SRD/SRC bit until it is set to 0x1. But looks like that bit is never set to 1 and there is an observable delay of 1sec everytime the driver tries to reset DAT/CMD. (The same is observed in linux kernel). Reduce the time the driver waits for the controller to set the SRC/SRD bits to 1 so that there is no observable delay. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
HS200/SDR104 requires tuning command to be sent to the card. Use the mmc_send_tuning library function to send the tuning command and configure the internal DLL. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
In order to enable DDR mode, Dual Data Rate mode bit has to be set in MMCHS_CON register. Set it here. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
Use the timing parameter set in the MMC core to set the mode in UHSMS bit field. This is in preparation for adding HS200 support in omap hsmmc driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
"ti,dual-volt" is used in linux kernel to set the voltage capabilities. For host controller dt nodes that doesn't have "ti,dual-volt", it's assumed 1.8v is the io voltage. This is not always true (like in the case of beagle-x15 where the io lines are connected to 3.3v). Hence if "no-1-8-v" property is set, io voltage will be set to 3v. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Kishon Vijay Abraham I 提交于
No functional change. Move bus width configuration setting to a separate function and invoke it only if there is a change in the bus width. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Jean-Jacques Hiblot 提交于
Add a separate function for starting the clock, stopping the clock and setting the clock. Starting the clock and stopping the clock can be used irrespective of setting the clock (For example during iodelay recalibration). Also set the clock only if there is a change in frequency. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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由 Masahiro Yamada 提交于
Use pr_* log functions from Linux. They can be enabled/disabled via CONFIG_LOGLEVEL. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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- 18 2月, 2018 9 次提交
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由 Marek Vasut 提交于
The 'reset' command did not work on Porter because the reset code was accessing the wrong PMIC address over broken I2C bus driver. Replace the code with DM-aware code and fix up the PMIC address. This makes the 'reset' command work again. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Get rid of the SH I2C driver on Porter and enable the IIC driver instead . The old SH I2C is completely broken on Porter anyway and the DM/DT capable IIC driver allows access to the PMIC too. Use the DM/DT capable driver instead. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Enable I2C6 bus on Porter to access the PMIC , ie. to reset the board. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The IIC on Gen2 is compatible with this driver as well, allow it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Set those limits to inform U-Boot about FDT and initramfs placement. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Enable cache and time commands, which are convenience tools for doing benchmarks and various boot tests. Also enable FIT support for booting fitImage. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Toggle the PHY reset GPIO to bring the ethernet PHY out of reset properly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- NOTE: This should be moved to the SH ethernet driver, but it's quite late in the cycle, so this is something to be done in 2018.05.
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由 Marek Vasut 提交于
Fix ommission where the u-boot,dm-pre-reloc DT bit was pulled into the common DT, not the U-Boot specific DT part. Move it to U-Boot DT part. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 17 2月, 2018 5 次提交
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由 Goldschmidt Simon 提交于
With multiple environments, the 'get_char' callback for env drivers does not really make sense any more because it is only supported by two drivers (eeprom and nvram). To restore single character loading for these drivers, override 'env_get_char_spec'. Signed-off-by: NSimon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
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由 York Sun 提交于
Commit 7d714a24 ("env: Support multiple environments") added static variable env_load_location. When saving environmental variables, this variable is presumed to have the value set before. In case the value was set before relocation and U-Boot runs from a NOR flash, this variable wasn't writable. This causes failure when saving the environment. To save this location, global data must be used instead. Signed-off-by: NYork Sun <york.sun@nxp.com> CC: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 16 2月, 2018 10 次提交
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由 Marek Vasut 提交于
This makes the shell so much more pleasant to use, so enable it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Due to size limitations of the MERAM, switch U-Boot to SPL. The SPL is loaded by the SPI_LOADER into MERAM and then loads U-Boot proper into DRAM. This way U-Boot can freely grow in size in DRAM, as there is plenty of it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- NOTE: To update U-Boot, first install u-boot.img to 0x140000 in SPI NOR, then use the Minimon to flash u-boot-spl.srec using ls,2,e6304000. To generate u-boot-spl.srec, use objcopy: arm-linux-gnueabi-objcopy -O srec spl/u-boot-spl u-boot-spl.srec
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由 Marek Vasut 提交于
Those two nodes are needed to configure pinmux before relocation and to configure clock before relocation, since CPG/MSSR needs access to RST node. This is not noticable on Gen3, but on Gen2 this causes problems in SPL if they are not available early. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Make the SCIF available before relocation and in SPL on R8A7791 Porter. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Cosmetic change, replace CONFIG_* with CONFIG_IS_ENABLED(*) . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
This makes the shell so much more pleasant to use, so enable it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Enable support for applying DT overlays on Gen3. This is convenient for handling extra additional hardware, like ie. the Kingfisher. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Reset and initialize the PHY once in the probe() function rather than doing it over and over again is start() function. This requires us to keep the clock enabled while the driver is in use. This significantly reduces the time between transfers as the PHY doesn't have to restart autonegotiation between transfers, which takes forever. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Joe Hershberger <joe.hershberger@ni.com>
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由 Marek Vasut 提交于
The SD driver calls clk_set_rate() before clk_enable(), yet clk_set_rate() implementation in the clock driver does not set the SD-IF divider. Fix it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 15 2月, 2018 1 次提交
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由 Alexander Graf 提交于
Commit 958d55f2 ("MAINTAINERS: Take over BCM2835 maintainership") put me in as maintainer for the RPi soc, but forgot to update the board MAINTAINERS file. Add me there too. Signed-off-by: NAlexander Graf <agraf@suse.de>
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