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  1. 11 10月, 2009 2 次提交
    • L
      Add bb_miiphy_init call before any ethernet bring-up code. · 310cecb8
      由 Luigi 'Comio' Mantellini 提交于 
      Signed-off-by: NLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
      310cecb8
    • L
      Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an... · 4ba31ab3
      由 Luigi 'Comio' Mantellini 提交于 
      Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses.

This feature is useful when your board uses different mii buses for different
phys and all (or a part) of these buses are implemented via bit-banging mode.

The driver requires that the following macros should be defined into the board
configuration file:

CONFIG_BITBANGMII       - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support

If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:

MII_INIT      - Generic code to enable the MII bus (optional)
MDIO_DECLARE  - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE   - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ     - Read the MDIO pin
MDIO(v)       - Write v on the MDIO pin
MDC_DECLARE   - Declaration needed to access to the MDC pin (optional)
MDC(v)        - Write v on the MDC pin

The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).

When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):

char name[]            - The symbolic name that must be equal to the MII bus
                         registered name
int (*init)()          - Initialization function called at startup time (just
                         before the Ethernet initialization)
int (*mdio_active)()   - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)()      - Write the MDIO pin
int (*get_mdio)()      - Read the MDIO pin
int (*set_mdc)()       - Write the MDC pin
int (*delay)()         - Delay function
void *priv             - Private data used by board specific code

The board code will look like:

struct bb_miiphy_bus bb_miiphy_buses[] = {
 { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... },
 { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... },
 ...
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
                          sizeof(bb_miiphy_buses[0]);
Signed-off-by: NLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
      4ba31ab3
  3. 09 10月, 2009 1 次提交
  5. 08 10月, 2009 4 次提交
    • J
      relocation: Do not relocate NULL pointers. · afc3ba0f
      由 Joakim Tjernlund 提交于 
      NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.
Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
      afc3ba0f
    • P
      85xx: Ensure BSS segment isn't linked at address 0 · 3beb40c2
      由 Peter Tyser 提交于 
      When U-Boot is relocated from flash to RAM pointers are modified
accordingly.  However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value.  If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.

This is a temporary workaround.  The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime.  When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
      3beb40c2
    • D
      tqm5200: Correct comment and code in post_hotkeys_pressed. · 95c44ec4
      由 Detlev Zundel 提交于 
      This fixes the code and the comment according to the original intent of
doing an intensive memory test when PSC6_3 is pulled low on the STK52xx.
Notably PORT_CONFIG will be overridden with this correct code now,
so beware.

The original code only worked by coincidence depending on the PORT_CONFIG
setting from the header file.  The new code was tested to ensure that the
(undocumented) memory test still works on the STK52x.
Signed-off-by: NDetlev Zundel <dzu@denx.de>
CC: Martin Krause <Martin.Krause@tqs.de>

Minor white-space cleanup.
Signed-off-by: NWolfgang Denk <wd@denx.de>
      95c44ec4
    • W
      mpc512x: fix fixed_sdram() init code. · da01f534
      由 Wolfgang Denk 提交于 
      Commit 054197ba and later fixes used an array to initialize some of
the MDDRC parameters; however, the use of an array turned out to be a
bad idea as it was not possible to correlate structure entries to
array indices in readable and reliable way. Now we use a struct
instead, which makes this self-explanatory.
Signed-off-by: NWolfgang Denk <wd@denx.de>
      da01f534
  7. 07 10月, 2009 7 次提交
  9. 05 10月, 2009 7 次提交
  11. 04 10月, 2009 2 次提交
  13. 03 10月, 2009 14 次提交
  15. 02 10月, 2009 3 次提交
    • M
      ppc4xx: Add SDRAM detection for PMC440 boards · 3b4bd2d7
      由 Matthias Fuchs 提交于 
      This patch adds support to detect the amount of DDR2 SDRAM
on PMC440 modules. Detection is done by probing through
a list of available and supported hardware configurations
from 1GByte down to 256MB.

The static TLB entry is replaced by dynamically created entries.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>
      3b4bd2d7
    • S
      ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling · fb95169e
      由 Stefan Roese 提交于 
      This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.

Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.

Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
      fb95169e
    • F
      ppc4xx: Reorganize DDR2 ECC handling · d24bd251
      由 Felix Radensky 提交于 
      Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.
Signed-off-by: NFelix Radensky <felix@embedded-sol.com>
Signed-off-by: NStefan Roese <sr@denx.de>
      d24bd251