- 25 10月, 2008 5 次提交
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由 Kumar Gala 提交于
PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NAndrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: NWolfgang Denk <wd@denx.de>
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由 Dave Liu 提交于
The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: NDave Liu <daveliu@freescale.com>
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由 Dave Liu 提交于
Signed-off-by: NDave Liu <daveliu@freescale.com>
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由 Kumar Gala 提交于
Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 22 10月, 2008 12 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Richard Retanubun 提交于
This is done to allow other 83XX based platforms which also have UPM (e.g. 8360) to configure and use their UPM in u-boot. Signed-off-by: NRichard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
We'll use these masks to parse TSEC modes out of HRCWH. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
MPC837xE specs says that SerDes1 has: — Two lanes running x1 SGMII at 1.25 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. And for SerDes2: — Two lanes running x1 PCI Express at 2.5 Gbps; — One lane running x2 PCI Express at 2.5 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. The spec also explicitly states that PEX options are not valid for the SD1. Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX, which is wrong to do. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Wolfgang Denk 提交于
On some systems (for example Fedora Core 4) U-Boot builds with the following wanrings only: ... In file included from /home/wd/git/u-boot/include/libfdt_env.h:33, from fdt.c:51: /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead! This patch fixes this problem. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 21 10月, 2008 15 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Dirk Eibach 提交于
Signed-off-by: NDirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Niklaus Giger 提交于
I reorganized my config files, putting the common stuff into netstal-common.h (got the idea by looking a amcc-common.h from Stefan). Added stuff to boot the new powerpc linux via NFS (only tested with HCU4). Signed-off-by: NNiklaus Giger <niklaus.giger@netstal.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Adam Graham 提交于
Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: NAdam Graham <agraham@amcc.com> Signed-off-by: NVictor Gallardo <vgallardo@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Adam Graham 提交于
This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: NAdam Graham <agraham@amcc.com> Signed-off-by: NVictor Gallardo <vgallardo@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Adam Graham 提交于
The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: NAdam Graham <agraham@amcc.com> Signed-off-by: NVictor Gallardo <vgallardo@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
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由 Wolfgang Denk 提交于
Several customers have reported problems with the environment in EEPROM, including corrupted content after board reset. Probably the code to prevent I2C Enge Conditions is not working sufficiently. We move the environment to flash now, which allows to have a backup copy plus gives much faster boot times. Also, change the default console initialization to 115200 bps as used on most other boards. Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Kumar Gala 提交于
mpc8536ds.c: In function 'is_sata_supported': mpc8536ds.c:615: warning: unused variable 'devdisr' Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
Round clock frequencies for printing. Many boards printed off clock frequencies like 399 MHz instead of the exact 400 MHz because numberes were not rounded. This is fixed now. Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Timur Tabi 提交于
Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot to add a comment that the correct value disagrees with the 8544 reference manual. The changelog for that commit is also wrong, as it says "bit 28" when it should be "bit 24". Signed-off-by: NTimur Tabi <timur@freescale.com>
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- 19 10月, 2008 8 次提交
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由 Wolfgang Denk 提交于
Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Heiko Schocher 提交于
Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Heiko Schocher 提交于
Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Jason Jin 提交于
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
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由 Liu Yu 提交于
This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: NLiu Yu <yu.liu@freescale.com>
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由 Liu Yu 提交于
The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: NLiu Yu <yu.liu@freescale.com>
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由 Ed Swarthout 提交于
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
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由 Ed Swarthout 提交于
Debug sessions may have left enabled laws. Changing lawbar with an unkown enabled tgtid could cause problems. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
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