- 07 12月, 2013 1 次提交
-
-
由 Masahiro Yamada 提交于
The lower 5 bit of MVBAR is UNK/SBZP. So, Monitor Vector Base Address must be 32-byte aligned. On the other hand, the secure monitor handler does not need 32-byte alignment. This commit moves ".algin 5" directive to the correct place. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: NAndre Przywara <andre.przywara@linaro.org>
-
- 06 12月, 2013 10 次提交
-
-
由 Albert ARIBAUD 提交于
-
由 Albert ARIBAUD 提交于
-
由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
-
由 Roger Quadros 提交于
Fixes this error message when USB is started. "ULPI: ulpi_reset: failed writing reset bit" It is pointless to manually reset the ULPI as the USB Host Reset and PHY RESET line should take care of that. Reported-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Fixes this error message when USB is started. "ULPI: ulpi_reset: failed writing reset bit" It is pointless to manually reset the ULPI as the USB Host Reset and PHY RESET line should take care of that. Reported-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
In commit bb1f327d we removed the UHH reset to fix NFS root (over usb ethernet) problems with Beagleboard (3530 ES1.0). However, this seems to cause USB detection problems for Pandaboard, about (3/8). On further investigation, it seems that doing the UHH reset is not the cause of the original Beagleboard problem, but in the way the reset was done. This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based on the UHH_REVISION register. This should fix the Beagleboard NFS problem as well as the Pandaboard USB detection problem. Reported-by: NTomi Valkeinen <tomi.valkeinen@ti.com> CC: Stefan Roese <sr@denx.de> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Michael Trimarchi 提交于
This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
-
由 Minkyu Kang 提交于
arndale board is booted from mmc Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Inderpal Singh <inderpal.singh@linaro.org>
-
由 Minkyu Kang 提交于
This patch fix following errors and warnings spl_boot.c: In function 'exynos_spi_copy': spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function) spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function) spl_boot.c: In function 'copy_uboot_to_ram': spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable] spl_boot.c: At top level: spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function] Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
-
由 Albert ARIBAUD 提交于
-
- 05 12月, 2013 8 次提交
-
-
由 Jaehoon Chung 提交于
These defines didn't use anywhere. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Acked-by: NAlexey Brodkin <abrodkin@synopsys.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
-
由 Jaehoon Chung 提交于
The "int" type is right. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
-
由 Vladimir Koutny 提交于
In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts. Signed-off-by: NVladimir Koutny <vladimir.koutny@streamunlimited.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
-
由 Hardik Patel 提交于
Signed-off-by: NHardik Patel <hardik.patel@volansystech.com>
-
由 Viktar Palstsiuk 提交于
MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: NViktar Palstsiuk <viktar.palstsiuk@promwad.com>
-
由 Stefan Roese 提交于
Enable FDT support for all Siemens AM335x boards. To support newer Linux kernels with DT booting. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher<hs@denx.de>
-
由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
-
由 Michael Trimarchi 提交于
This patch add the OMAP34XX_UART4 memory address Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
-
- 04 12月, 2013 20 次提交
-
-
由 Lokesh Vutla 提交于
Certain EFUSE settings were recommended for the first four lots of OMAP5 ES1.0 silicon. These are not applicable for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings. Reported-by: NGriffis, Brad <bgriffis@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
-
由 Roger Quadros 提交于
The evm has a SATA port. Enable SATA configuration and inititialize the SATA controller. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Adds the necessary PRCM and Control register information for SATA on DRA7xx. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
The uevm has a SATA port. Inititialize the SATA controller. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Add platform glue logic for the SATA controller. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Align the ATA ID buffer to the cache-line boundary. This gets rid of the below error mesages on ARM v7 platforms. scanning bus for devices... ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818 CC: Aneesh V <aneesh@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
If malloc() fails, we don't want to continue in ahci_init() and ahci_init_one(). Also print a more informative error message on malloc() failures. CC: Rob Herring <rob.herring@calxeda.com> Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 SRICHARAN R 提交于
When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: NSricharan R <r.sricharan@ti.com>
-
由 SRICHARAN R 提交于
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: NSricharan R <r.sricharan@ti.com>
-
由 SRICHARAN R 提交于
A generic is_dra7xx cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: NSricharan R <r.sricharan@ti.com>
-
由 Tom Rini 提交于
Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: NTom Rini <trini@ti.com> Tested-by: NMatt Porter <matt.porter@linaro.org>
-
由 Oleg Kosheliev 提交于
Added chip type detection and twl6032 support in the battery control and charge functions. Based on Balaji T K <balajitk@ti.com> patches for TI u-boot. Signed-off-by: NOleg Kosheliev <oleg.kosheliev@ti.com>
-
由 Oleg Kosheliev 提交于
The data struct is used to support different PMIC chip types. It contains the chip type and the data (e.g. registers addresses, adc multiplier) which is different for twl6030 and twl6032. Replaced some hardcoded values with the structure vars. Based on Balaji T K <balajitk@ti.com> patches for TI u-boot. Signed-off-by: NOleg Kosheliev <oleg.kosheliev@ti.com>
-
由 Lubomir Popov 提交于
The struct incorrectly referenced SMPS1 for all three power domains. Fixed this by using SMPS2 and SMPS5 as appropriate. Add some comments and choose voltage values that correspond to voltage selection codes. Signed-off-by: NLubomir Popov <l-popov@ti.com>
-
由 Lars Poeschel 提交于
Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on the board. The difference for u-boot is that is has other DDR3 RAM on it: 1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and 2. Both configurations are 512 MiB. Configure your u-boot build with pcm051_rev3 for the new RAM and pcm051_rev1 for the old RAM configuration. Board revision 2 has to use pcm051_rev1 also. Signed-off-by: NLars Poeschel <poeschel@lemonage.de>
-
由 Ilya Ledvich 提交于
Add support for the 16 bits pca9555 i2c to gpio extender featured by the SB-T335 baseboard. Signed-off-by: NIlya Ledvich <ilya@compulab.co.il> Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
-
由 Ilya Ledvich 提交于
Add support for status LED. Use the STATUS_LED APIs for indicating a boot progress. Signed-off-by: NIlya Ledvich <ilya@compulab.co.il> Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
-
由 Ilya Ledvich 提交于
Add cm_t335 board directory, config file. Enable build. Signed-off-by: NIlya Ledvich <ilya@compulab.co.il> Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> [trini: Adapt Makefile] Signed-off-by: NTom Rini <trini@ti.com>
-
- 03 12月, 2013 1 次提交
-
-
由 Chin Liang See 提交于
Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
-