- 18 12月, 2015 9 次提交
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由 Marek Vasut 提交于
This function is local to s3c_udc_otg_xfer_dma.c , staticize it. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_request to reflect this. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_ep to reflect this. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_dev_*_ep to reflect this. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy to make things more obvious and clear. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
Most of the functions are local to the s3c_udc driver, remove them from the s3c_udc.h header to stop those bits from propagating all over the place. Instead, move all the private stuff into new private s3c_udc_otg_priv.h header. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg to make things more obvious and clear. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_udc to struct dwc2_udc to make things more obvious and clear. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
Rename the header file, so it's obvious which driver it's part of. No functional change. Signed-off-by: NMarek Vasut <marex@denx.de>
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- 16 12月, 2015 2 次提交
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由 Alexey Brodkin 提交于
This fixes commit 1a37889b: ----------------------->8-------------------- eeprom: Pull out the RW loop Unify the code for doing read/write into single function, since the code for both the read and write is almost identical. This again trims down the code duplication. ----------------------->8-------------------- where the same one routine is utilized for both EEPROM writing and reading. The only difference was supposed to be a "read" flag which in both cases was set with 1 somehow. That lead to a missing delay in case of writing which lead to write failure (in my case no data was written). Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Acked-by: NMarek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de>
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由 York Sun 提交于
This reverts commit e8f954a7, which causes compiling errors on 32-bit hosts. Acked-by: NAneesh Bansal <aneesh.bansal@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 15 12月, 2015 17 次提交
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由 Tang Yuantian 提交于
Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Stein 提交于
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: NAlexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves some memory from the end of ram, tracked by gd->ram_size. It is not always the top of u-boot visible memory. Rewrite the macro with a weak function to provide flexibility for complex calcuation. Legacy use of this macro is still supported. Signed-off-by: NYork Sun <yorksun@freescale.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 York Sun 提交于
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc. This is different from PRAM used to reserve private memory. PRAM offers memory at the top of u-boot memory, not necessarily the real end of memory for systems with very large DDR. Using the end of memory simplifies MMU setup and avoid memory fragmentation. "bdinfo" command shows gd->secure_ram value if this memory is marked as secured. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Yao Yuan 提交于
As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Yao Yuan 提交于
This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Yao Yuan 提交于
Enable snoop and DVM message on all CCI-400 slave ports. Setting on disabled feature (snoop or DVM) is ignored by CCI-400. Signed-off-by: NYuan Yao <yao.yuan@freescale.com> [York Sun: Add commit message] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tom Rini 提交于
Since the changes in a1e56cf6 the way that we had board_mmc_init() structured for OMAP parts (so that we always report device 0) are no longer functional. For now, make the case of booting from the second device initialize both devices (we have no devices that only have the second device as MMC). A further rework and consolidation of the functions should be done at a later date. Tested on Beaglebone Black (SD and eMMC boot). Reported-by: NVagrant Cascadian <vagrant@debian.org> Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Eric Nelson 提交于
In order to support boot from multiple devices through board_boot_order, it's necessary to use the block number of a device. The use of a hard-coded 0 for the device number also creates a need to re-order block devices for use in SPL like this: http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195Signed-off-by: NEric Nelson <eric@nelint.com>
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- 14 12月, 2015 12 次提交
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由 Yao Yuan 提交于
Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Yao Yuan 提交于
Create a soc.c file to put the code for soc special settings. Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tom Rini 提交于
With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and becomes BUG_ON((!a) != b). In this case reading of the function leads to us wanting to rewrite this as BUG_ON(a != b). Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com> Cc: Haiying Wang <Haiying.Wang@freescale.com> Cc: Roy Pledge <Roy.Pledge@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tom Rini 提交于
GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun <yorksun@freescale.com> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
This patch also expose the complete DDR region(s) to Linux. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaohui Xie 提交于
When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: NYork Sun <yorksun@freescale.com>
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