- 22 2月, 2014 1 次提交
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由 Dave Gerlach 提交于
Schematic indicates GPIO5_7 is to be used for VTT regulator control rather than GPIO0_21 so modify enable_vtt_regulator to reflect this. Without this some boards will experience DDR3 corruption and fail to boot. Signed-off-by: NDave Gerlach <d-gerlach@ti.com> [trini: Rework patch against mainline] Signed-off-by: NTom Rini <trini@ti.com>
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- 25 1月, 2014 1 次提交
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由 Lokesh Vutla 提交于
This patch enables dynamically powering down the IO receiver when not performing a read on DDR3 board. This optimizes both active and standby power consumption. This is derived from a patch that is done on AM335x[1] [1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4bc72ece53fabf01825605fba3d71d5feb2Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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- 19 12月, 2013 6 次提交
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由 Lokesh Vutla 提交于
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Sekhar Nori 提交于
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the board. These variables are used by findfdt. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Sekhar Nori 提交于
Add support for reading onboard EEPROM to enable board detection. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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- 15 8月, 2013 2 次提交
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由 Lokesh Vutla 提交于
Add dpll and clock data for AM43xx Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add board specific information for AM43xx. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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