The MMC spec says "It is strongly recommended for hosts to implement
more than 500ms timeout value even if the card indicates the 250ms
maximum busy length."  Even the previous value of 300ms is known to
be insufficient for some cards. So, increase the timeout to 500ms.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.

Guard against their usage by hiding the bit mask macros on those
processors.

These bits are used to prevent glitches when changing clocks on
i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.

>From the i.MX6DQ RM:
	To prevent possible glitch on the card clock, clear the
	FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
	or DVS in System Control Register) or setting RSTA bit.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Reviewed-by: NHector Palacios <hector.palacios@digi.com>

When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

If adapter card type identification is supported for platform, we would
enable dat[4:7] for eMMC4.5 Adapter Card.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

commit b8e5b072 "Powerpc: eSDHC: Fix mmc read write err in uboot of
T4240QDS board", T4160 also needs this fix.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds esdhc support for ls1043ardb.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This function is called from esdhc_send_cmd so we need it available to
everyone.
Signed-off-by: NTom Rini <trini@konsulko.com>

DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.

We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.

With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Signed-off-by: NYe.Li <B37916@freescale.com>
Signed-off-by: NNitin Garg <nitin.garg@freescale.com>
Signed-off-by: NJason Liu <r64343@freescale.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>

Freescale eMMC44 adapter card uses Micron N2M400FDB311A3CF eMMC
memory. According to the silicon datasheet, secure erase timeout
is 600ms. So increase erase timeout value from 250ms to 600ms.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>

High capacity support is not a host capability, but a device capability
that is queried via the OCR. The flag in the operating conditions
request argument can just be set unconditionally. This matches the Linux
implementation.

[panto] Hand merged and renumbering MMC_MODE_DDR_52MHz.
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NPantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>

The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for T1024/T1040/T2080. To enable it, define
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
[York Sun: resolve conflicts in README.fsl-esdhc]
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds esdhc support for ls2085a.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Commit f022d36e introduces
error register offset.

Change the "char reserved3[59]" to "char reserved3[56]".
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.
Signed-off-by: NVolodymyr Riazantsev <volodymyr.riazantsev@globallogic.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Some boards cannot do voltage negotiation but need to set the VSELECT
bit forcely to ensure it to work at 1.8V.

This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>

This adds support to switch to 1.8V in case CMD11 succeeds.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Reviewed-by: NMarek Vasut <marex@denx.de>

U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NPavel Machek <pavel@denx.de>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Tested-by: NLukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: NTom Rini <trini@ti.com>

The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0
on iMX6SX. So the fsl_esdhc driver must update to set the register,
otherwise no state can be detected.
Signed-off-by: NYe.Li <B37916@freescale.com>

for multi instance API we use struct fsl_esdhc_cfg to
pass the clock rate. Do not set f_max from global data,
since this is wrong for multi instance case.
Signed-off-by: NMarkus Niebel <Markus.Niebel@tq-group.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Tested-by: NEric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The macro MIN, MAX is defined as the aliase of min, max,
respectively.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.

For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>

In 71689776 we made calls to check_and_invalidate_dcache_range()
conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO.  Only define this function
in this case as well.
Signed-off-by: NTom Rini <trini@ti.com>

When configure the fsl_esdhc driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.

Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data in cache was
overwritten by physical memory.
2. The watermarks are not set in PIO mode, will cause according state not
be set.
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NYe.Li <B37916@freescale.com>

T4240RDB board Specification
----------------------------
Memory subsystem:
   6GB DDR3
   128MB NOR flash
   2GB NAND flash

Ethernet:
   Eight 1G SGMII ports
   Four 10Gbps SFP+ ports

PCIe:
   Two PCIe slots

USB:
   Two USB2.0 Type A ports

SDHC:
   One SD-card port

SATA:
   One SATA port

UART:
   Dual RJ45 ports
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]

1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.

2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.

* Update of patch for change mmc interface by
	Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.
Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

The way that struct mmc was implemented was a bit of a mess;
configuration and internal state all jumbled up in a single structure.

On top of that the way initialization is done with mmc_register leads
to a lot of duplicated code in drivers.

Typically the initialization got something like this in every driver.

	struct mmc *mmc = malloc(sizeof(struct mmc));
	memset(mmc, 0, sizeof(struct mmc);
	/* fill in fields of mmc struct */
	/* store private data pointer */
	mmc_register(mmc);

By using the new mmc_create call one just passes an mmc config struct
and an optional private data pointer like this:

	struct mmc = mmc_create(&cfg, priv);

All in tree drivers have been updated to the new form, and expect
mmc_register to go away before long.

Changes since v1:

* Use calloc instead of manually calling memset.
* Mark mmc_register as deprecated.
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Using an array is pointless; even more pointless (and scary) is using
sprintf to fill it without a format string.
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Remove the in-structure ops and put them in mmc_ops with
a constant pointer to it.

This makes the mmc structure smaller as well as conserving
code space (in theory).

All in-tree drivers are converted as well; this is done in a
single patch in order to not break git bisect.

Changes since V1:
Fix compilation b0rked issue on omap platforms where OMAP_GPIO was
not set.
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>

The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.
Signed-off-by: NHaijun Zhang <haijun.zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
   For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.

This workaround force sdhc driver scan and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T4240QDS eSDHC host capabilities reigster should have VS33 bit define.
Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity
missing
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

struct mmc should be clear to all '0' after malloc to avoid
unexpect variable value.

Like mmc->has_init = xxx.
In this case mmcinfo will believe the card had been initialized before
and skip the initialization.

Test on P5040 and T4240,
Error Log:

=> mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 0-bit
=>
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
Signed-off-by: NXie Shaohui-B21989 <B21989@freescale.com>
Tested-by: NRyan Barnett <rjbarnet@rockwellcollins.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Add some descriptions for esdhc register for easily using.
Signed-off-by: NHaijun Zhang <haijun.zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0.
Signed-off-by: NHaijun Zhang <haijun.zhang@freescale.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

malloc can fail, so we should better check its return value before using it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

Dealing with the sys ctrl register should touch only the
relevant bits and not accidently the whole register. On i.MX6,
the sys control register contains bits which shouldn't be reset to
0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).

Do this by read/modify/write instead of just a 32bit write.
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NAndy Fleming <afleming@freescale.com>