Enable DM SATA in board file.
Signed-off-by: NTony Dinh <mibodhi@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Add DM_ETH, SATA_MV and associated configs to goflexhome_defconfig.
Signed-off-by: NTony Dinh <mibodhi@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

u-boot-imx-20210809

- new SOC: add support for imx8ulp
- Toradex fixes for colibri (vf / imx6 / imx7 / imx8x)
- convert to DM for mx28evk
- Fixes for Gateworks ventana boards

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639

Use log subsystem for dm_warn()
Various minor bug fixes

cmd_tbl_t is removed, need use struct cmd_tbl
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART

Log as below: I would keep some debug info for now, and after we move
to be stable and production launch, we could drop that.

U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
Normal Boot
upower_init: soc_id=48
upower_init: version:11.11.6
upower_init: start uPower RAM service
user_upwr_rdy_callb: soc=b
user_upwr_rdy_callb: RAM version:12.6
Turn on switches ok
Turn on memories ok
Clear DDR retention ok
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F0 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
complete
De-Skew PLL is locked and ready
WDT:   Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x3a800 by ROM_API
NOTICE:  BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94
NOTICE:  BL31: Built : 01:56:58, Jun 29 2021
NOTICE:  upower_init: start uPower RAM service
NOTICE:  user_upwr_rdy_callb: soc=b
NOTICE:  user_upwr_rdy_callb: RAM version:12.6

U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)

CPU:   Freescale i.MX8ULP rev1.0 at 744 MHz
Reset cause: POR
Boot mode: Single boot
Model: FSL i.MX8ULP EVK
DRAM:  2 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... ***
Warning - bad CRC, using default environment

In:    serial@293a0000
Out:   serial@293a0000
Err:   serial@293a0000
Net:
Warning: ethernet@29950000 (eth0) using random MAC address -
96:35:88:62:e0:44
eth0: ethernet@29950000
Hit any key to stop autoboot:  0
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8ULP dtsi
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.

When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init
Signed-off-by: NYe Li <ye.li@nxp.com>

Add upower api support, this is modified from upower firmware exported
package.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Move struct mu_type to common header to make it reusable by upower and
S400
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

When booting from boot part1/2, the image offset should be 0, but
ROM has a bug to return 0x8000. Has to workaround the issue before
ROM fix it.

Use a ROM function to know boot from emmc boot part or user part
So we can set the image offset accordingly.
Signed-off-by: NYe Li <ye.li@nxp.com>

Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian,
it does not connect to low 16 bits for RTD. So we can't get the correct
boot mode.
Change to use DGO_GP5 of SEC_SIM which is set by ROM.
Signed-off-by: NYe Li <ye.li@nxp.com>

The CMC1 SRS reflects the current reset cause, not SSRS.

Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot.
Reviewed-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

This driver uses FSB to read some fuses, but not support program fuse.
It only works in SPL (secure mode), u-boot needs traps to ATF to
read them.

Some fuses can read from S400 API and others are from FSB.
Also support program some fuses via S400 API
Signed-off-by: NYe Li <ye.li@nxp.com>

Add i.MX8ULP iomuxc support
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add imx_get_mac_from_fuse for enet build pass
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Configure DCNANO and MIPI_DSI to be controlled by AD for single boot
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Read from ROM API to get current boot device.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Need probe the S400 MU device in arch_cpu_init_dm, so we can use
S400 API in u-boot
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Unify rdc function to rdc.c
Update soc.c to use new rdc function
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Rlease LPAV from RTD to APD
Release gpu2D/3D to APD
Set TRDC MBC2 MEM1 for iomuxc0 access
Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c
and MODE pins. we have to open iomuxc0 access for A35 core (domain 7)
in single boot.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Signed-off-by: NYe Li <ye.li@nxp.com>

Add TRDC release request, then we could configure resources to be
accessible by A35 Domain.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

There is xrdc inside i.MX8ULP, we need to configure permission to make
sure AP non-secure world could access the resources.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.

1. Set the parameters save/restore only for u-boot, not for SPL. to
   avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
   to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add API to support fuse read and write
Signed-off-by: NYe Li <ye.li@nxp.com>

The RDC API is updated to add a field for XRDC or TRDC
Signed-off-by: NYe Li <ye.li@nxp.com>

Add S400 API for image authentication
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

According to latest S400 API doc, the the success indicate value is
changed to 0xd6. So update the driver codes.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Because we have set reset vector to ATF in SPL, have to set it back
to ROM for any reset in u-boot
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Disable wdog3 which is configured by ROM
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.

So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

CMC1 also has a MR register for bootcfg
Signed-off-by: NYe Li <ye.li@nxp.com>

i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8ULP clock support
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8ULP lpuart has same register layout as i.MX7ULP and i.MX8
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add pinctrl driver for i.MX8ULP
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Support i.MX8ULP in fec_mxc
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NRamon Fried <rfried.dev@gmail.com>

Add MU driver and S400 API. Need enable MISC driver to work
Signed-off-by: NYe Li <ye.li@nxp.com>

Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig
public to both.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>