CONFIG_ENV_SIZE for NAND was later in this file overwritten
because we have the environment in i2c eeprom, so remove
this define.
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

commit 010a958b
(arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h)
breaks building keymile arm targets, when u-boot.kwb tries to
generate the binary with mkimage. A simple make <board> or MAKEALL
succeeded because it don't try to build the kirwood binary at the end.

Due this commit we use the CONFIG_SYS_KWD_CONFIG from the
arch-kirkwood/config.h and it was removed from the board config.
But it was forgotten to include the header. Now the header is included
in km_arm.h. Some other defines were obsolete due to this include,
these are also removed in this commit.
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

Some boards e.g. keymile arm boards have CONFIG_CMD_I2C switched on
but they use soft i2c on kirkwood. So don't switch CONFIG_I2C_MVTWSI
on in this case.
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>

* Fix compiler error for cpu at91sam9, if lowlevel init is enabled
* use correct ATMEL_ name scheme to define ATMEL_BASE_SDRAMC

Signed-off-by: Jens Scharsig

This patch removes the board implemenatation for flash driver which can now
safely switched to the common cfi driver.

Compile tested for all atstk100x boards, runtime tested on atstk1002.
Signed-off-by: NAndreas Bießmann <biessmann@corscience.de>

The at91rm9200_usart driver could be fully replaced by atmel_usart driver.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Cc: Eric Bénard <eric@eukrea.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
Acked-by: Jens Scharsig<js_at_ng@scharsoft.de>
Tested-by: Jens Scharsig<js_at_ng@scharsoft.de> (for eb_cpux9k2 board)

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This is a copy of arm926ejs/at91 api for perpherial initialisation.
At the moment we just need the usart part of the api.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch enables the new clock features from arm920t/at91/clock.c. This
is an required step to get at91rm9200_usart replaced by atmel_usart driver.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Cc: Jens Scharsig <js_at_ng@scharsoft.de>
Cc: Eric Bénard <eric@eukrea.com>

This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The
arm926ejs specialities are removed from arm920t version and vice versa.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch sets the ATMEL_PMX_AA_TXD2 to the correct value.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
CC: eric@eukrea.com
Acked-by: NEric Bénard <eric@eukrea.com>

commit 0015de1a (MX5: Make the weim structure complete) fixed the name for
the WEIM registers in order to match with the MX51/MX53 manuals.

Fix the WEIM register for vision2 board so that it can build again.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Enable dcache and arch memset/memcpy for speed reasons
Remove of config.mk and some environment overwrites
Some generic cleanup
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

Define CONFIG_SYS_SDRAM_BASE to physical SDRAM address
and CONFIG_SYS_INIT_SP_ADDR to physical SRAM address
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Cc: Kyungmin Park <kyungmin.park@samsung.com>

As implemented now the timer used to implement __udelay counts
to 0xffffffff and then gets stuck there because the the programmed
reload value is 0xffffffff.  This value is not only wrong but
illegal according to the reference manual.

One can reproduce the bug by leaving a board at the u-boot prompt
for sometime then issuing a sleep command.  The sleep will hang
forever.

The timer is a count up timer that reloads as it rolls over
from 0xffffffff so the correct load value is 0.

Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce
a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff.
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>

Signed-off-by: NTom Warren <twarren@nvidia.com>

Signed-off-by: NTom Warren <twarren@nvidia.com>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

adapt s5pc1xx to the new layered cache maintenance framework
Signed-off-by: NAneesh V <aneesh@ti.com>

adapt omap3 to the new layered cache maintenance framework
Signed-off-by: NAneesh V <aneesh@ti.com>

adapt omap4 to the new layered cache maintenance framework
Signed-off-by: NAneesh V <aneesh@ti.com>

PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430

Add support for some of the key PL310 operations
	- Invalidate all
	- Invalidate range
	- Flush(clean & invalidate) all
	- Flush range
Signed-off-by: NAneesh V <aneesh@ti.com>

1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
   than a range flush on the entire memory(flush_cache())

   Provide a default implementation for flush_dcache_all()
   for backward compatibility and to avoid build issues.
Signed-off-by: NAneesh V <aneesh@ti.com>

- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
	- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
	- Make changes according to the new framework
Signed-off-by: NAneesh V <aneesh@ti.com>

Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF
Signed-off-by: NAneesh V <aneesh@ti.com>
V2:
 * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message

- Add a framework for layered cache maintenance
	- separate out SOC specific outer cache maintenance from
	  maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
  caches known to ARMv7 CPUs. For instance in Cortex-A8 these
  opertions will affect both L1 and L2 caches. In Cortex-A9
  these will affect only L1 cache

- D-cache operations supported:
	- Invalidate entire D-cache
	- Invalidate D-cache range
	- Flush(clean & invalidate) entire D-cache
	- Flush D-cache range
- I-cache operations supported:
	- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
  used
Signed-off-by: NAneesh V <aneesh@ti.com>

make default implementation of cache_flush() weakly linked so that
sub-architectures can override it
Signed-off-by: NAneesh V <aneesh@ti.com>

On MPC85xx based NAND_SPL builds we generate a u-boot-nand_spl.lds based
on output from preprocessor.  We where never removed it.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NScott Wood <scottwood@freescale.com>

This patch adds support for 16 bit NAND devices attached to the
NDFC on ppc4xx processors. Two config entries were added:

  CONFIG_SYS_NDFC_16        - Setting this tells the NDFC that a
			      16 bit device is attached.
  CONFIG_SYS_NDFC_EBC0_CFG  - This is for the External Bus
			      Controller configuration register.

Also, a new ndfc_read_byte() function was added which does not
first convert the data to little endian.

The NAND SPL was also modified to do 16bit bad block testing
when a 16 bit chip is being used.
Signed-off-by: NAlex Waterman <awaterman@dawning.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Add another nand write. variant, trimffs. This command will request of
nand_write_skip_bad() that all trailing all-0xff pages will be
dropped from eraseblocks when they are written to flash as-per the
reccommended behaviour of the UBI FAQ [1].

The function that implements this timming is the drop_ffs() function
by Artem Bityutskiy, ported from the mtd-utils tree.

[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algoSigned-off-by: NBen Gardiner <bengardiner@nanometrics.ca>
CC: Artem Bityutskiy <dedekind1@gmail.com>
CC: Detlev Zundel <dzu@denx.de>
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Add a flag to nand_read_skip_bad() such that if true, any trailing
pages in an eraseblock whose contents are entirely 0xff will be
dropped.

The implementation is via a new drop_ffs() function which is
based on the function of the same name from the ubiformat
utility by Artem Bityutskiy.

This is as-per the reccomendations of the UBI FAQ [1]

[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algoSigned-off-by: NBen Gardiner <bengardiner@nanometrics.ca>
CC: Artem Bityutskiy <dedekind1@gmail.com>
Acked-by: NDetlev Zundel <dzu@denx.de>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an
operation which is mutually exclusive with the 'usual' way of writing.

Add a check that client code does not specify WITH_YAFFS_OOB along with any
other flags and add a comment indicating that the WITH_YAFFS_OOB flag should
not be mixed with other flags.
Signed-off-by: NBen Gardiner <bengardiner@nanometrics.ca>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>