The i2c uclass has a default setting for per_child_platdata_auto_alloc_size
so drivers do not need to set it. Remove this from drivers to avoid
confusion.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Currently, only the CPU_ON function is supported.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This invalidates entries in specified ways of the outer cache.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line
length and its tags are also managed per 128 byte line.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM.  The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it.  It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Commit 4b50369f ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.

The idea here is to check the current page table to determine if
it is a straight map table.  If not, adjust the outer cache register
base.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable().  The weak
stub avoids the compile error anyway.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.

These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.

This reduces the code duplication.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Adjust this driver to support driver model for Ethernet.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>

Change the prototype of a few functions to allow resuing the code for
the driver model.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>

Commit "ecc30663 Fix board init code to respect the C runtime environment"
broke platform support for ppc4xx.
start.S prepares a stackframe that is later rendered unusable by appending
the reserved space for global data.
Instead the reserved space has to be put first. Then the stackframe can
be pushed.

I can only test the 405EP OCM case. At least all other ppc4xx boards still
build.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: NStefan Roese <sr@denx.de>

As I2C can be used before DRAM initialization for reading EEPROM,
avoid using static variables stored in BSS, since BSS is in DRAM, which
may not have been initialised yet. Explicitly mark "static global"
variables as belonging to the .data section.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: Heiko Schocher<hs@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When a target device is 0 bytes long, there's no point in exposing it to
the user. Let's just skip them.

Also, when an offset is passed into the efi disk creation, we should
remove this offset from the total number of sectors we can handle.

This patch fixes both things.
Signed-off-by: NAlexander Graf <agraf@suse.de>

When using CONFIG_BLK, there were 2 issues:

  1) The name we generate the device with has to match the
     name we set in efi_set_bootdev()

  2) The device we pass into our block functions was wrong,
     we should not rediscover it but just use the already known
     pointer.

This patch fixes both issues.
Signed-off-by: NAlexander Graf <agraf@suse.de>

We can pass all the variables down to the functions that need them, and
then everything is on the stack. This is safer than using the data section.

At least on firefly-rk3288, the code size is the same and the data size is
12 bytes smaller:

before:
  18865	   2636	     40	  21541	   5425	b/firefly-rk3288/spl/u-boot-spl
after:
  18865	   2624	     40	  21529	   5419	b/firefly-rk3288/spl/u-boot-spl
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NStefan Roese <sr@denx.de>

There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Keystone net can have multiple ethernet slaves, currently only
slave 1 is supported by the driver. Register multiple slaves as
individual ethernets to network framework.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Each line should be terminated by semi-colon. It was not caught
earlier as there is a proper statement. Fix it by changing the
comma with semi-colon.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

PCF8575 does not have any registers hence, offset field needs to be
ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len
with 0 in PCF8575 DT nodes.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

On DRA7, pcf chip present at address 0x21 on i2c1, is used to
switch between cpsw slave0 and slave1. Hence, enable PCF
driver for the same.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os should be high before being used as inputs.
Read the device documentation for more details[1].

This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.

[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdfSigned-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

The devicetrees for various platforms already exceed 16k. Add a define
CONFIG_SYS_FDT_SIZE to specify the FDT size, and set to 16k for the
two boards that define this CONFIG_SYS_FDT_BASE parameter. This
allows platforms with larger devicetree blobs to boot from NOR.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>

In asix_recv() the call to convert the endianess of the receive header
was applied on the wrong variable. Instead of converting rx_hdr it
converted pkt_hdr which is a pointer, and not yet initialiazed at this
point.
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>

Added support for the Cypress GX3 SuperSpeed to Gigabit Ethernet
Bridge Controller (VID_04b4/PID_3610).
Signed-off-by: NAlban Bedel <alban.bedel@avionic-design.de>

Enables driver model flag CONFIG_DM_USB for LS1021A
platform defconfigs.
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>

Update USB 3.0 controller dts node in ls1021a.dtsi.
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>