When copying the command line buffer the target array should
at least have the same size.

Cf. definition of console_buffer in common/cli_readline.c.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

use ALLOC_CACHE_ALIGN_BUFFER_PAD for mbr header allocation
in stack to fix alloc issue in is_gpt_valid()

this patch fix also issue for GPT partition handling
with blocksize != 512 in set_protective_mbr()
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>

Add a header for SAMA5D2 SMC since it's not compatible with
SAMA5D3 one.
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>
[wenyou: fix the wrong base address of the SMC register]
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>

The capabilities have default values which doesn't reflect the reality
when it concerns the base clock and the mul value. Use a fixe rate
for the gck. 240 MHz is an arbitrary choice, it is a multiple of the
maximum SD clock frequency handle by the controller and it allows to
get a 400 kHz clock for the card initialisation.
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>

Differentiate the generic clock source selection value from the parent
clock index to fix the incorrect assignment of the generic clock
source selection.
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>

To get the same behavior as the Linux driver, instead of selecting
the closest inferior rate, select the closest inferior or superior
rate
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>

What the AT91_UTMI depends on SPL_DM isn't right. AT91_UTMI is not
only used in SPL, also in other place, even if SPL_DM isn't enabled.
Signed-off-by: NWenyou Yang <wenyou.yang@microchip.com>

MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family
and used a common MPU's region config.

Only one exception for STM32H7 which doesn't have device area
located at 0xA000 0000.

For STM32F4, configure_clocks() need to be moved from arch_cpu_init()
to board_early_init_f().
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.

STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.
Signed-off-by: NChristophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

This allows to add rcc MFD support to stm32f746-disco board
This rcc MFD driver manages clock and reset for STM32 SoCs family
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

STM32F4 doesn't get rcc.h file, to avoid compilation
issue, migrate RCC related defines from rcc.h to driver
file and remove rcc.h file.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

STM32F4 and STM32F7 RCC clock IP are very similar.
Same driver can be used to managed RCC clock for
these 2 SoCs.

Differences between STM32F4 and F7 will be managed using
different compatible string :
 _ overdrive clock is only supported by STM32F7
 _ different sys_pll_psc parameters can be used between STM32F4
   and STM32F7.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

Add a dedicated stm32f7 compatible string to use clk_stm32f7
driver with both STM32F4 and STM32F7 SoCs.
It will be needed to manage differences between these 2 SoCs.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

This node is needed to enable performance mode
when system frequency is set up to 200Mhz.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

Up to now we were able to read/write environment data from/to UBI
volumes only indirectly by gluebi driver. This driver creates NAND MTD
on top of UBI volumes, which is quite a workaroung for this use case.

Add support for direct read/write UBI volumes in order to not use
obsolete gluebi driver.

Forward-ported from this patch:
http://patchwork.ozlabs.org/patch/619305/

Original patch:
Signed-off-by: NMarcin Niestroj <m.niestroj@grinn-global.com>

Forward port:
Signed-off-by: NS. Lockwood-Childs <sjl@vctlabs.com>

AE3XX can not support SD high-speed mode.
SW can work-around by removing HS capibility.
Signed-off-by: NRick Chen <rick@andestech.com>

Bit of DATA_END and DATA_CRC_OK shall be checked for
returning pass or fail of a request.
Signed-off-by: NRick Chen <rick@andestech.com>

AG101P/AE3XX enable ftsdc010 dm flow.
Signed-off-by: NRick Chen <rick@andestech.com>

Add dts to support ftsdc010 dm flow on AG101P/AE3XX platform.
Signed-off-by: NRick Chen <rick@andestech.com>

ftsdc010 support device tree flow.
Signed-off-by: NRick Chen <rick@andestech.com>

Add nds32_mmc to support ftsdc010 dm flow.
Signed-off-by: NRick Chen <rick@andestech.com>

Add a document to describe Andestech atcspi200 spi and
binding information.
Signed-off-by: NRick Chen <rick@andestech.com>

Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.
Signed-off-by: NRick Chen <rick@andestech.com>

atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.
Signed-off-by: NRick Chen <rick@andestech.com>

ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.
Signed-off-by: NRick Chen <rick@andestech.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add a document to describe Andestech atcpit100 timer and
binding information.
Signed-off-by: Nrick <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use dev_get_platdata to get private platdata.
Signed-off-by: Nrick <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Integrate function and struct name as atcpit100 will be
more reasonable.
Signed-off-by: Nrick <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.
Signed-off-by: Nrick <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.
Signed-off-by: NRick Chen <rick@andestech.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support

This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>