we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Commit f29f804a generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
CC: Scott Wood <scottwood@freescale.com>

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFO
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NHarninder Rai <harninder.rai@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c
Signed-off-by: NTom Rini <trini@ti.com>

Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ.
It should be CONFIG_TIMER_CLK_FREQ.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
[York Sun: This is the difference between two patch versions]
Reviewed-by: NYork Sun <yorksun@freescale.com>

As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

'eccstat' array elements might be used uninitialized
Signed-off-by: NJaiprakash Singh <b44839@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.

Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.

This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.

This patch adds BE mode support for smp pen address.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Check USB Erratum A007792 applicability. If applicable, add
corresponding  property in the device tree via device tree fixup
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.

The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The SD/NAND/QSPI boot definations are wrong for QE support, this
patch is to fix this error.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch will fix the bug that the partitions on the SD card could
not be accessed and add the support for the FAT fs.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: NChen Lu <chen.lu@freescale.com>
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NJason Jin <jason.jin@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NJason Jin <jason.jin@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: NJason Jin <jason.jin@freescale.com>
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add SUPPORT_SPL feature for SD and NAND boot on
LS1021AQDS and LS1021ATWR.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds to fix the issue about
using I2C in SPL.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For LS102xA, the size of spl/u-boot-spl.bin is variable.
This patch adds the support to deal with the variable
u-boot size in pblimage tool. It will be padded to 64
byte boundary.

Use pblimage_check_params() to add the specific operations
for ARM, such as PBI CRC and END command and the calculation
of pbl_cmd_initaddr.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.
Signed-off-by: NChenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.
Signed-off-by: NChenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The bus frequency in SOC node should be clock frequency of platform.
That is not true if it is devided by 2.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Alt board has been connected to eMMC of 8GB to MMC port.
This enables MMC port and MMC command.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>