This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).

There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This commit removes the dram reservation from board file,
because it is done in a common code.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This commit enables the last DRAM bank and reserves
the last 22 MiB of it, for the secure firmware.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Hyungwon Hwang <human.hwang@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Since more than one board requires memory reservation
for the secure firmware, the reservation code can be
made in a common code.
Now, to reserve some part of the the last bank,
board config should define:
- CONFIG_TZSW_RESERVED_DRAM - len in bytes
- CONFIG_NR_DRAM_BANKS - number of memory banks
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Hyungwon Hwang <human.hwang@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch suppress following warning:

board/samsung/common/board.c:95:32: warning: iteration 4u invokes undefined behavior [-Waggressive-loop-optimizations]
   addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
                                ^
board/samsung/common/board.c:94:2: note: containing loop

about possible signed integer overflow at gcc 4.8.2 (odroid board)
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NSinan Akman <sinan@writeme.com>

Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This code was introduced to support the multiple .config
configuration in U-Boot.  We do not need it any more.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Fix trivial typo.
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NAxel Lin <axel.lin@ingics.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

With a3895314 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.
Signed-off-by: NTom Rini <trini@konsulko.com>

After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.

Such patch formalizes current development status.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>

Integrate latest validated register settings from Toradex WinCE BSP
4.2 working accross all module versions from early V1.x, V1.2D, V2.2B
to V2.4A.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Usually not required for NOR flash.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

While 'mmc init' is no longer required the address to bootm the kernel
from NOR flash was wrong.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Specify a CONFIG_BOARD_SIZE_LIMIT of 256 KB in order to avoid
overwriting the factory configuration block located at offset 0x40000
in NOR flash.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

To save more than 20 KB of precious space in NOR flash get rid of the
following configuration options:

CONFIG_CMD_LOADB
CONFIG_CMD_LOADS
CONFIG_SYS_LONGHELP
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Migrate Toradex Colibri PXA270 to use CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

I couldn't quite figure out whether or not CONFIG_SYS_ENV_IS_NOWHERE
actually ever worked but nowadays this is called CONFIG_ENV_IS_NOWHERE.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Basically finish what the following commit started a long time ago:

488f5d87Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

For mx35pdk/woodburn:
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs.  The line
size is still 128 byte.  Thus, the way size is 32KB/64KB for old/new
SoCs.

To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB.  It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.

The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority.  Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Two support card variants are used with UniPhier reference boards:
 - 1 chip select support card (original CPLD)
 - 3 chip selects support card (ARIMA-compatible CPLD)

Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously.  Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>