U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.

Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:

repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]

According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.

At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.

An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.

While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.

Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Marcel Ziswiler <marcel@ziswiler.com>
Cc: Bard Liao <bardliao@realtek.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.

A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE

1) It isn't documented in README. The same is true for a lot of similar
   defines used by api_storage.c.

2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
   valid values are 0..n-1 not 0..n.

However, I this patch does not address those shortcomings.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

 - expand the condition with CONFIG_OF_CONTROL
Signed-off-by: NStephan Linz <linz@li-pro.net>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Last argument shouldn't be there.
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Acked-by: NMarek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>

Preprocessor definitions and hardcoded implementation selection in
g_dnl core were replaced by a linker list made of (usb_function_name,
bind_callback) pairs.
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NMarek Vasut <marex@denx.de>

Future patches will make DFU too large to fit in this board's SPL build.
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Acked-by: NTom Rini <trini@ti.com>
Reviewed-by: NLukasz Majewski <l.majewski@samsung.com>

Previously offsets handled by dfu_fill_entity_mmc(), defined in boards'
CONFIG_DFU_ALT were treated as hexadecimal regardless of their prefix,
which sometimes led to confusion. This patch forces usage of explicit
numerical base prefixes.
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Cc: Tom Rini <trini@ti.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>

When user attempted to perform a raw write using DFU (vide
dfu_fill_entity_mmc) with MMC interface not initialized before,
get_mmc_blk_size() reported invalid (zero) block size - it wasn't
possible to write ie. a new u-boot image.

This commit fixes that by initializing MMC device before use in
dfu_fill_entity_mmc().

While fixing initialization sequence, I had to change about half of
dfu_fill_entity_mmc's body, so I refactored it on the way to make it,
IMHO, considerably more comprehensible.

Being left as dead code, get_mmc_blk_size() was removed.

Tested on Samsung Goni.
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Acked-by: NTom Rini <trini@ti.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>

Former usb_cable_connected() patch broke compilation of boards which do
not support this feature.

I've renamed usb_cable_connected() to g_dnl_usb_cable_connected() and added
its default implementation to gadget downloader driver code. There's
only one driver of this kind and it's unlikely there'll be another, so
there's no point in keeping it in /common.

Previously this function was declared in usb.h. I've moved it, since
it's more appropriate to keep it in g_dnl.h - usb.h seems to be intended
for USB host implementation.

Existing code, confronted with default -EOPNOTSUPP return value,
continues as if the cable was connected.

CONFIG_USB_CABLE_CHECK was removed.

Change-Id: Ib9198621adee2811b391c64512f14646cefd0369
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NLukasz Majewski <l.majewski@samsung.com>

Implementation made use of types defined in common.h, even though it
wasn't #included. It worked in circumstances when .c files included
every needed header (all).
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Cc: Tom Rini <trini@ti.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>

Structure definition used type block_dev_desc_t, defined in part.h, which
wasn't included in mmc.h. It worked only in circumstances when common.h,
or another header using part.h was incuded in implementation files.

Change-Id: I5b203928b689887e3e78beb00a378955e0553eb7
Signed-off-by: NMateusz Zalega <m.zalega@samsung.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>

Since highbank is actually shared between Highbank and Midway platforms,
remove the Highbank name from the prompt and use the default.
Signed-off-by: NRob Herring <robh@kernel.org>

Adapt highbank to use config_distro_defaults.h and remove the redundant
defines.
Signed-off-by: NRob Herring <robh@kernel.org>

This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

With 32 milliseconds delay on some boards EEMPROM got written inconsistently.
With 64 msec all of our existig boards show properly written EEPROM.

Cc: Tom Rini <trini@ti.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

add support for the ids8313 board.

CPU:   e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz
I2C:   ready
SPI:   ready
DRAM:  128 MiB (DDR2, 32-bit, ECC off, 264 MHz)
Flash: 8 MiB
NAND:  128 MiB
Net:   TSEC0, TSEC1 [PRIME]

public key on NOR flash start
Signed-off-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
  ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
  previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.

In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc

The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.

get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.

Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

U-boot binary size has been increased from 512KB to 768KB.

So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
      - Add spl.c which defines board_init_f, board_init_r
      - update tlb and ddr accordingly
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
  - Add spl.c which defines board_init_f, board_init_r
  - update tlb and ddr accordingly
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1042RDB_PI board does not have QE connector.

So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add u-qe support for t1040qds
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add deep sleep support on T104xRDB platforms.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add deep sleep support on T1040QDS platform.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.

Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header file
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

NOR flash is on CS1 instead of CS2 when NAND boot.
So correct NOR chip selection to CS1 from CS2.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>