Add imximage-8mp-lpddr4.cfg for imximage usage, almost same
as i.MX8MN ddr4 cfg, but with different ddr firmware
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8MP clk driver for i.MX8MP CLK driver model usage
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add imx_clk_mux2_flags which will be used by i.MX8MP
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

The drivers/clk/imx/*.c are used for CLK dm case, the
clock_imx8mm.c is used for non CLK dm case, let's split
it. Sometimes it is hard to enable CLK dm in SPL stage,
considering code size, malloc size requirement, the splittion
will make it easy to use non CLK dm in SPL stage.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8MP ROM support ROMAPI as i.MX8MN, so make
SPL_IMX_ROMAPI_LOADADDR visible to i.MX8MP
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8MP does not have LVTTL, it has a PE property
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add pin header file for i.MX8MP
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: NRobin Gong <yibin.gong@nxp.com>
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

The i.MX8M Plus Media Applications Processor is part of the growing
mScale family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in Samsung 14LPP to achieve both
high performance and low power consumption and relies on a powerful
fully coherent core complex based on a quad core ARM Cortex-A53 cluster
and Cortex-M7 low-power coprocessor, audio digital signal processor,
machine learning and graphics accelerators.

Add the basic dtsi support for i.MX8MP.

Patch from Anson Huang for Kernel
https://patchwork.kernel.org/patch/11310915/Signed-off-by: NPeng Fan <peng.fan@nxp.com>

We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8MP compatible to let the pinctrl driver could support
i.MX8MP.
Reviewed-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

4000MTS DDR needs 1GHz fracpll, so add the entry
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8MP has similar architecture as i.MX8MN, but it has different
clk root and index, so add that to make i.MX8MP could use
the non-dm clock driver.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8MP pinfunc header for dts usage
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add i.MX8MP clock header
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8MP follows i.MX8MN, so just let it use spl_board_boot_device
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add Kconfig entry for i.MX8MP
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

i.MX8MP use 0x182 as dummy id, 0xFF is not able the get the highest
bit, so enlarge bit mask to 0x1FF to make it could detect
cpu type correctly
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Support get i.MX8MP cpu id and cpu type
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK +
dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK
as root clk and cause sd card could not be detected in U-Boot proper,
as below:
"Loading Environment from MMC... unable to select a mode"

Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Tested-by: NBaruch Siach <baruch@tkos.co.il>
Tested-by: NFabio Estevam <festevam@gmail.com>

After the conversion to DM_PMIC the following output is seen:

PMIC:  PMIC:  PFUZE100 ID=0x10

Remove the unnecessary PMIC string from the board file to
avoid the repetead string.
Signed-off-by: NFabio Estevam <festevam@gmail.com>

Commit ec837c82 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:

CPU:   Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM:  2 GiB
PMIC:  pmic_get() ret -19
...

and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:

WARNING: Could not determine dtb to use

and the kernel does not boot at all.

Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.

Fixes: ec837c82 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: NFabio Estevam <festevam@gmail.com>

It's true that booting normally doesn't take long enough for the
register to roll (which actually happens in a little over an hour, not
just a few seconds). However, the counter starts at power-on, and if
the board is held in reset to be booted over USB, one actually risks
hitting wrap-around during boot, which can both result in too short
delays (if the "st += delay" calculation makes st small) and
theoretically also unbound delays (if st ends up being UINT_MAX and
one just misses sampling digctl_microseconds at that point).

It doesn't take more code to DTRT, and once bitten, twice shy.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.

So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.

Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on
the 1.5 version of the i.Core MX6 cpu module. The 1.5 version
differs from the original one for a few details, including the
ethernet PHY interface clock provider.

With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver

While before using the 1.5 version, ethernet failed to startup
do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY

Similar fix has merged for i.Core MX6Q but missed to update for DL.
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Sync Engicam device tree file from v5.4 linux-next.
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Now all the fec related phy properties are now accessible
via dts. So drop the explicit config items from common
config file, imx6-engicam.h
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

According to the SOM and reference board the clock
can be taken from the external pin or provided from
ENET_REF_CLK. Add a new function that make the proper
set according the board type.
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Make easy to map fdt file to board in order to use
this information later to apply specific change to
specific board combination.
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then
busy-waiting for it to actually clear. My board hung. The data sheet
agrees, these registers do not have _set, _clr, _tog, so fix up the
definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody
uses those non-existing ops registers.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

Adjust the environment for booting a mainline kernel by default.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

Add info about supported i.MX7, improve details the usage of
bcbonly subcommand.
Signed-off-by: NIgor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>

When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: NIgor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: NIgor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: NIgor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.

Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.
Signed-off-by: NFrieder Schrempf <frieder.schrempf@kontron.de>