- 16 7月, 2011 1 次提交
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由 Tom Warren 提交于
Signed-off-by: NTom Warren <twarren@nvidia.com> Acked-by: NAndy Fleming <afleming@freescale.com>
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- 12 7月, 2011 26 次提交
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由 Ramneek Mehresh 提交于
Move to use hwconfig for usb mode & phy type instead of magic 'usb_phy_type' environment variable on the following platforms: MPC8536DS, P1020RDB, P1020RDB-PC, P1010RDB, P2020RDB, P2020RDB-PC, P2020RDB, P3041DS, P4080DS, & P5020DS. Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Enable buffer write for better performance. This platform uses a NOR flash chip which supports write buffer programming. CFI driver can query the buffer size and use it to program the flash for best performance. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a bank soft-reset after the bank was configured and enabled, even though enabling a bank causes it to reset. Because the reset was required for multiple errata, it was not properly enclosed in an #ifdef, and so was not removed with all the other rev1 errata work-arounds. Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if bank 2 is enabled, but this was not being done for SERDES protocols 0xF and 0x10. The bank reset also happened to enable bank 3 (apparently an undocumented feature). Simply removing the reset breaks these two protocols. It turns out that every time we call enable_bank(), we do want at least one lane of the bank enabled, either because the bank is supposed to be enabled, or because we need the clock from that bank enabled. For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we call enable_bank(), because that array is used elsewhere to determine if the bank is available. Note that the side effect of these changes is that the work-arounds for these two errata are now linked. Specifically, if SERDES-A001 is enabled, then we need SERDES-8 enabled as well. Because this was the only SERDES bank soft-reset, there is no need to implement a work-around for erratum SERDES-A003. Also fix an off-by-one error in a printf(). Signed-off-by: NTimur Tabi <timur@freescale.com> Acked-by: NEd Swarthout <swarthou@freescale.com> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Ramneek Mehresh 提交于
Resolve P1020 second USB controller multiplexing with eLBC - mandatory to mention USB2 in hwconfig string to select it over eLBC, otherwise USB2 node is removed - works only for SPI and SD boot Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Ramneek Mehresh 提交于
Specify hwconfig usage for USB mode and phy change Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Ramneek Mehresh 提交于
Modify support for USB mode fixup: - Add common support for USB mode and phy type device tree fix-up for all USB controllers mentioned in hwconfig string - Fetch USB mode and phy type via hwconfig; if not defined in hwconfig, then fetch them from env Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Roy Zang 提交于
The P1023RDS board is the reference board for the P1023 SoC. Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe, UART, I2C, etc. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: NLei Xu <B33228@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
If DDR initialziation uses a speed table and the speed is not matched, print a warning message instead of silently ignoring. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Allow overriding RCW for all RDIMM, not only quad-rank ones. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
In case of empty SPD or checksum error, fallback to raw timing on supported boards. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Felix Radensky 提交于
On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: NFelix Radensky <felix@embedded-sol.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Adding byte 32 and 33 Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 York Sun 提交于
If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Shaohui Xie 提交于
When booting from NAND we get the environment and FMan ucode from NAND. Signed-off-by: NShaohui Xie <b21989@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
The P2041 is similar to P2040, however has a 10G port and backside L2 Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Mingkai Hu 提交于
Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Add ifdef protection for qp_info and liodn associated with Q/BMan. Also rearrange setting of _tbl_sz variables to utilize existing ifdef protection for things like FMAN. Also add protection around setup_portals() call in corenet_ds board code. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Ramneek Mehresh 提交于
Add CONFIG_HAS_FSL_DR_USB macro for P1020RDB Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Add ifdef protection in LBC code to handle the case in which CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a build. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Add ifdef protection in LAW & TLB code to handle the case in which CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a build. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 07 7月, 2011 7 次提交
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由 Bill Cook 提交于
On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: NBill Cook <cook@isgchips.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Timur Tabi 提交于
Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Andre Schwarz 提交于
Includes board config file, documentation, maintainer and boards.cfg entries, and board specific files in vendor dir. Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Andre Schwarz 提交于
CPO value and driver strength settings are board specifc. Also allow SPD data fetch from any accessible I2C EEPROM. Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Andre Schwarz 提交于
Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Andre Schwarz 提交于
Running on mpc837x without CONFIG_FSL_ESDHC leads to i2c1_clk not being set at all. It is bound to clock of encryption module. fix this. Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Ira W. Snyder 提交于
Commit 359ec493 broke support for the Freescale DMA engine on the 83xx parts. This is due to using registers which do not exist on 83xx. Remove the attribute register accesses from the 83xx build. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Cc: York Sun <yorksun@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 04 7月, 2011 6 次提交
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由 Simon Guinot 提交于
This patch add support for the Network Space v2 board and parents, based on the Marvell Kirkwood 6281 SoC. This include Network Space (Max) v2 and Internet Space v2. Additional information is available at: http://lacie-nas.org/doku.php?id=network_space_v2Signed-off-by: NSimon Guinot <sguinot@lacie.com>
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由 Valentin Longchamp 提交于
This adds support for the keymile Kirkwood BEC portl2 board. This board relies on the km_arm (km_kirkwood) BEC. The egiga driver is configured for a 100M full-duplex, A/N off connnection to the backplane. This board has always ethernet present, because it is connected to the marvell switch similar to mgcoge3un. The reset_phy functionality is also the same to mgcoge3un. Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
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由 Holger Brunck 提交于
suen3 and suen8 were in first HW version quite different, but now they are from a u-boot point of view similar. So these two boards can use the same header file. Other keymile boards differ only in the usage of the PCI interface. Therefore a target km_kirkwood_pci was introduced. All targets use the same header file. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
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由 Valentin Longchamp 提交于
The phy is also configured with "RGMII clock transitions when data stable" and "Class A driver for the direct backplane connection". Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
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由 Valentin Longchamp 提交于
This is defined for all km_kirkwood boards and was not used up to now. This value was the same for all boards but it could be changed for some boards (and thus needs to be defined for every board). Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
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由 Holger Brunck 提交于
CONFIG_ENV_SIZE for NAND was later in this file overwritten because we have the environment in i2c eeprom, so remove this define. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
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