- 25 5月, 2021 1 次提交
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由 Simon Glass 提交于
There is no good reason to use a sequence from rand() here. We may as well invent our own sequence. This should molify Coverity which does not use rand() being used. Signed-off-by: NSimon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 312949)
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- 24 5月, 2021 1 次提交
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由 Tom Rini 提交于
Clang has -Wself-assign enabled by default under -Wall and so when building with -Werror we would get an error here. Inspired by Linux kernel git commit a21151b9d81a ("tools/build: tweak unused value workaround") make use of the fact that both Clang and GCC support casting to `void` as the method to note that something is intentionally unused. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 23 5月, 2021 1 次提交
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https://source.denx.de/u-boot/custodians/u-boot-sh由 Tom Rini 提交于
- Various clk/pinctrl updates to re-sync with Linux and other fixes
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- 21 5月, 2021 16 次提交
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由 Marek Vasut 提交于
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it. Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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- 20 5月, 2021 13 次提交
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https://source.denx.de/u-boot/custodians/u-boot-marvell由 Tom Rini 提交于
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors)
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由 Stefan Roese 提交于
With commit 8678776d (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Vladimir Vid <vladimir.vid@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Marcin Wojtas 提交于
Until now the mvpp2 driver used an extra 'phy-speed' DT property in order to differentiate between the SGMII and SGMII @2.5GHz. As there is a dedicated PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter start using it and drop the custom flag. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Tested-by: NNadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Stefan Chulski 提交于
Currently, there are 2 valid cases for interface, PHY and mdio relation: - If an interface has PHY handler, it'll call mdio_mii_bus_get_from_phy(), which will register MDIO bus. - If we want to use fixed-link for an interface, PHY handle is not defined in the DTS, and no MDIO is registered. There is a third case, for some boards (with switch), the MDIO is used for switch configuration, but the interface itself uses fixed link. This patch allows this option by checking if fixed-link subnode is defined, in this case, MDIO bus is registers, but the PHY address is set to PHY_MAX_ADDR for this interface, so this interface will not try to access the PHY later on. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ben Peled 提交于
Signed-off-by: NBen Peled <bpeled@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Ben Peled 提交于
Signed-off-by: NBen Peled <bpeled@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Ben Peled 提交于
Signed-off-by: NBen Peled <bpeled@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
GMII_SPEED should be enabled for 2.5G speed Signed-off-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NYan Markman <ymarkman@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marcin Wojtas 提交于
Because the mvpp2 driver now relies on the PHYLIB and the external MDIO driver, configuring low level SMI bus settings is redundant. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Stefan Chulski 提交于
Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Stefan Chulski 提交于
1. Differ between Port1 RGMII and SFI modes in Netcomplex config. 2. Remove XPCS config from SFI mode. Port1 doesn't XPCS domain, XPCS config should be removed. Access to Port1 XPCS can cause stall. 3. Add Port1 MPCS configurations. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 19 5月, 2021 8 次提交
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https://source.denx.de/u-boot/custodians/u-boot-microblaze由 Tom Rini 提交于
Xilinx changes for v2021.07-rc3 ZynqMP: - Syncup DT with Linux kernel - Fix mmc mini configurations via DT - Add pinctrl/psgtr description to DTs - Add DTs for Kria boards - Enable RTC and Time commands Versal: - Fix early BSS section location
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由 Rick Chen 提交于
It will need larger heap size for u-boot-spl to load u-boot.itb which be generated from binman than USE_SPL_FIT_GENERATOR. Signed-off-by: NRick Chen <rick@andestech.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Now that we have switched to binman to generate u-boot.itb for all RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can be dropped. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs, so that binman is now used to generate u-boot.itb. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Bin Meng 提交于
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along with a new dedicated device tree source file for the QEMU virt target used for binman only, we can now use binman to generate u-boot.itb. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is provided in the U-Boot build phase hence the binman node information is not available. In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT is introduced, to tell the build system that a device tree blob containing binman node is explicitly required when using binman to package U-Boot. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. For the other OF_CONTROL methods, it's quite possible binman node is not available as binman is invoked during the build phase instead of runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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