- 17 3月, 2017 31 次提交
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由 Jagan Teki 提交于
BOOT_CFG1[7:4] the NAND boot mode selection is done only when BOOT_CFG1[7] is 1 hence update the NAND boot mode detection bit case. This information available on Table 8-11. NAND Boot eFUSE Descriptions, from IMX6DQRM. Cc: Tim Harvey <tharvey@gateworks.com> Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: NJagan Teki <jagan@openedev.com>
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由 Jagan Teki 提交于
For i.MX6, the bootmode determine code is part of spl_boot_device, but there is might be a possibility for other part the code need to check the desired boot mode for adding new functionalities like modeboot env variable, or changing boot order etc. So introduced imx6_src_get_boot_mode which actually reading the boot mode register for desired modes. More cleanup will be add in future patches. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@openedev.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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由 Jagan Teki 提交于
dts files related to i.MX6 engicam boards are maintined under board, so include them under board/engicam/*/MAINTAINERS Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable I2C support for Engicam Is.IoT NAND module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add config options for booting Linux from NAND in UBI format. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add NAND support for Engicam Is.IoT MX6UL board. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add FEC support for Engicam Is.IoT MX6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add FEC node for Engicam Is.IoT MX6UL module. Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: NStefano Babic <sbabic@denx.de> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C support for Engicam Is.IoT MX6UL module. isiotmx6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 isiotmx6ul> i2c dev 0 Setting bus to 0 isiotmx6ul> i2c dev Current bus is 0 isiotmx6ul> i2c speed 100000 Setting bus speed to 100000 Hz isiotmx6ul> i2c probe Valid chip addresses: 00 2C 44 78 isiotmx6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: NStefano Babic <sbabic@denx.de> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Add I2C nodes for Engicam Is.IoT MX6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Boot from MMC: ------------- U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33) Trying to boot from MMC1 U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 33C Reset cause: POR Model: Engicam Is.IoT MX6UL Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 isiotmx6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
USDHC base address will assigned by SPL using fsl_esdhc_initialize and u-boot with devicetree, hence no remove base address assignment in config files. Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: NStefano Babic <sbabic@denx.de> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Peng Fan 提交于
Enable MMC support. The fsl sdhc driver needs regulator to enable power, so enable regulator support. And bootcmd and more env. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add EVK board support. Add the evk dts file. LOG: U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800) CPU: Freescale i.MX7ULP rev1.0 at 500 MHz Reset cause: POR Boot mode: Dual boot Model: NXP i.MX7ULP EVK DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial@402D0000 Out: serial@402D0000 Err: serial@402D0000 Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add compatible property for i.MX7ULP. Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add i.MX7ULP dtsi file. Add clock and pinfun header files. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add i.MX7ULP support. The buadrate calculation on i.MX7ULP is different,so add a new setbrg function for i.MX7ULP. Add a enum lpuart_devtype for runtime check for different platforms. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
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由 Peng Fan 提交于
Drop CONFIG_LPUART_32B_REG. Move the register structure to a common file include/fsl_lpuart.h Define lpuart_serial_platdata structure which includes the reg base and flags. For 32Bit register access, use lpuart_read32/lpuart_write32 which handles big/little endian. For 8Bit register access, still use the orignal code. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
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由 Peng Fan 提交于
Add lpi2c driver for i.MX7ULP. Need to enable the two options to use this driver: CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y Signed-off-by: NPeng Fan <peng.fan@nxp.com> Acked-by: NHeiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Ye Li 提交于
This driver implements the HW WATCHDOG functions. Which needs to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for mx7ulp. Use watchdog for reset cpu. Implement this in the driver. Need to define CONFIG_ULP_WATCHDOG to build it. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Ye Li 提交于
Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Update the mxc_ocotp driver to support i.MX7ULP. The read/write sequence has some changes due to PDN and OUT_STATUS registers added and TIME register is removed. Also update the bank size and number. Add is_mx7ulp macro in sys_proto.h Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Ye Li 提交于
Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Reuse some code in imx-common. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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由 Peng Fan 提交于
i.MX7ULP is a new series SoC which has different architecture from previous i.MX platforms. Create a new cpu folder for it, and add it to Kconfig. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
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- 15 3月, 2017 9 次提交
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由 Masahiro Yamada 提交于
At first, the ARM64 Linux booting requirement recommended that the kernel image be placed text_offset bytes from 2MB aligned base near the start of usable system RAM because memory below that base address was unusable at that time. This requirement was relaxed by Linux commit a7f8de168ace ("arm64: allow kernel Image to be loaded anywhere in physical memory"). Since then, the bit 3 of the flags field indicates the tolerance of the kernel physical placement. If this bit is set, the 2MB aligned base may be anywhere in physical memory. For details, see Documentation/arm64/booting.txt of Linux. The booti command should be also relaxed. If the bit 3 is set, images->ep is respected, and the image is placed at the nearest bootable location. Otherwise, it is relocated to the start of the system RAM to keep the original behavior. Another wrinkle we need to take care of is the unknown endianness of text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16). We can detect this based on the image_size field. If the field is zero, just use a fixed offset 0x80000. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Richard reported U-Boot tools issues in OpenEmbedded/Yocto project. OE needs to be able to change the default compiler. If we pass in HOSTCC through the make command, it overwrites all HOSTCC instances, including ones in tools/Makefile and tools/env/Makefile, which breaks "make cross_tools" and "make env", respectively. Add "override" directives to avoid overriding HOSTCC instances that really need to point to the cross-compiler. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reported-by: NRichard Purdie <richard.purdie@linuxfoundation.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
These two functions are only used in lib/tiny-printf.c . Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Tested-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Ladislav Michl 提交于
Leave only detected flash type enabled in FTD as otherwise GPMC CS is claimed (and never freed) by Linux, causing 'concurent' flash type not to be probed. Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
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由 Ladislav Michl 提交于
ISEE's U-Boot and Linux are using 1bit ECC scheme, while we switched to 8bit ECC to fullfill flash specification requirements. However when trying to run U-Boot on board with 1bit ECC'd data on flash, UBI code takes several minutes to pass scan as reading of every block ends with ecc error (which is also printed on console). So, until proper solution is developed, disable environment alltogether. Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
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由 Patrice Chotard 提交于
This is a 96Board compliant board based on STiH410 SoC: - 1GB DDR - On-Board USB combo WiFi/Bluetooth RTL8723BU with PCB soldered antenna - Ethernet 1000-BaseT - SATA - HDMI - 2 x USB2.0 type A - 1 x USB2.0 type micro-AB - SD card slot - High speed connector (SD/I2C/USB interfaces) - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces) Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrice Chotard 提交于
This device tree has been extracted from v4.9 kernel Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrice Chotard 提交于
Add STMicroelectronics STiH410 pinctrl driver Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrice Chotard 提交于
Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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