Add device table for M70A series Micron SPI NAND devices.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add device table for M79A and M78A series Micron SPI NAND devices.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage
details as a comment.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

In order to add new Micron SPI NAND devices, we generalized the OOB
layout structure and function names.
Signed-off-by: NShivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

- dm: core: Don't show an ACPI warning if there is no ordering
- x86: Enhance MTRR functionality to support multiple CPUs

Update this command so it can list the MTRRs on a selected CPU. If
'-c all' is used, then all CPUs are listed.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

Add a description of how this module works and also some missing function
comments.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a -c option to mtrr to allow any CPU to be updated with this command.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present do_mtrr() does the 'list' subcommand at the top and the rest
below. Update it to do them all in the same place so we can (in a later
patch) add parsing of the CPU number for all subcommands.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Use the multi-CPU calls to set the MTRR values. This still supports only
the boot CPU for now.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

To enable support for the 'mtrr' command, add a way to perform MTRR
operations on selected CPUs.

This works by setting up a little 'operation' structure and sending it
around the CPUs for action.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

When the boot CPU MTRRs are updated, perform the same update on all other
CPUs so they are kept in sync.

This avoids kernel warnings about mismatched MTRRs.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This currently excludes the temporary memory used to start up the APs.
Add it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL.
For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot,
but this is somewhat more complicated. For now that is disabled too.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

Update the mtrr command to use mp_run_on_cpus() to obtain its information.
Since the selected CPU is the boot CPU this does not change the result,
but it sets the stage for supporting other CPUs.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It is convenient to iterate through the CPUs performing work on each one
and processing the result. Add a few iterator functions which handle this.
These can be used by any client code. It can call mp_run_on_cpus() on
each CPU that is returned, handling them one at a time.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

With the new MP features the CPUs are no-longer parked when the OS is run.
Fix this by calling a special function to park them, just before the OS is
started.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a way to run a function on a selection of CPUs. This supports either
a single CPU, all CPUs, just the main CPU or just the 'APs', in Intel
terminology.

It works by writing into a mailbox and then waiting for the CPUs to notice
it, take action and indicate they are done.

When SMP is not yet enabled, this just calls the function on the main CPU.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Set this flag so we can track when it is safe to use CPUs other than the
main one.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Allow keeping track of whether all CPUs have been enabled yet. This allows
us to know whether other CPUs need to be considered when updating
CPU-specific settings such as MTRRs on x86.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present the APs (non-boot CPUs) are inited once and then parked ready
for the OS to use them. However in some cases we want to send new requests
through, such as to change MTRRs and keep them consistent across CPUs.

Change the last state of the flight plan to go into a wait loop, accepting
instructions from the main CPU.

Drop cpu_map since it is not used.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Drop some #ifdefs that are not needed or can be converted to compile-time
checks.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This function is misnamed since it does not actually init the BSP. Also
it is convenient to adjust it to return a little more information.

Rename and update the function, to allow it to return the BSP CPU device
and number, as well as the total number of CPUs.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present each CPU is given a number when it starts itself up. While this
saves a tiny amount of time by doing the device-tree read in parallel, it
is confusing that the numbering happens on the fly.

Move this code into mp_init() and do it at the start.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Fix a typo in the command help.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This does not need to be global across all functions in this file. Pass a
parameter instead.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

These parameters are named differently from elsewhere in this file. Switch
them to avoid confusion.

Also add comments to this function.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

The functions used by the flight plan are declared in the header file but
are not used in any other file.

Move the flight plan steps down to just above where it is used so that we
can make these function static.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present the 'flight plan' for CPUs is passed into mp_init. But it is
always the same. Move it into the mp_init file so everything is in one
place. Also drop the SMI function since it does nothing. If we implement
SMIs, more refactoring will be needed anyway.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Update this code to use livetree calls instead of flat-tree.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Some boards don't care about the ordering of ACPI code fragments. Change
the warning to a debug message.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

- MIPS: refactor cache init and setup in start.S
- MIPS: sync asm header files with Linux 5.7
- MIPS: add initial support for Marvell Octeon MIPS64

This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.

Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the code to copy itself from bootrom location to a
different location (TEXT_BASE) to the Octeon platform. Its used in
this case to copy the complete U-Boot image into L2 cache, which
greatly improves the bootup time - especially in regard to the
very long and complex DDR4 init code.

The Kconfig symbol CONFIG_MIPS_MACH_EARLY_INIT is enabled with this
patch for Octeon.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

This patch adds the optional call to mips_mach_early_init() to start.S
at a very early stage. Its disabled per default. It can be used for
very early machine / platform specific init code.  Its called very
early and at this stage the PC is allowed to differ from the linking
address (CONFIG_TEXT_BASE) as no absolute jump has been performed until
this call.

It will be used by thje Octeon platform.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Sync asm/mipsregs.h with Linux 5.7. Also replace the custom
symbols EBASE_CPUNUM and EBASE_WG with the according symbols
from Linux.
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Tested-by: NStefan Roese <sr@denx.de>