- 16 1月, 2009 1 次提交
-
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
-
- 15 1月, 2009 2 次提交
-
-
由 Wolfgang Denk 提交于
Update CHANGELOG. Signed-off-by: NWolfgang Denk <wd@denx.de>
-
由 Wolfgang Denk 提交于
Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: NWolfgang Denk <wd@denx.de>
-
- 14 1月, 2009 9 次提交
-
-
由 Wolfgang Denk 提交于
-
-
由 Haiying Wang 提交于
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
-
由 Haiying Wang 提交于
So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
-
由 Roy Zang 提交于
The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
-
由 Roy Zang 提交于
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
-
由 Roy Zang 提交于
The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
-
由 Becky Bruce 提交于
Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
-
由 Becky Bruce 提交于
Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
-
- 12 1月, 2009 1 次提交
-
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
-
- 11 1月, 2009 1 次提交
-
-
- 07 1月, 2009 11 次提交
-
-
由 Mike Frysinger 提交于
The board_nand_init() function should return an int, not void. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
由 Mike Frysinger 提交于
The eeprom SPI init functions are duplicated as the common code already executes these for us. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
由 Mike Frysinger 提交于
Many of the Blackfin board linker scripts are preprocessed, so make sure we output the linker script into the build tree rather than the source tree. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
由 Mike Frysinger 提交于
Make sure all .text sections get pulled in and the entry point is properly referenced so they don't get discarded when linking with --gc-sections. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
由 Mike Frysinger 提交于
In order to boot an LDR out of parallel flash, the ldr utility needs a few flags to tell it to generate the right header. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
由 Nicolas Ferre 提交于
At91sam9xe is basically an at91sam9260 with embedded flash. We can manage it as another entry for at91sam9260 in the Makefile. Check documentation at : http://www.atmel.com/dyn/products/product_card.asp?part_id=4263Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
introduced in commit 89a7a87fSigned-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-
- 31 12月, 2008 5 次提交
-
-
-
-
-
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
-
- 30 12月, 2008 2 次提交
-
-
由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
-
由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
-
- 20 12月, 2008 8 次提交
-
-
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NRemy Böhmer <linux@bohmer.net>
-
由 Trent Piepho 提交于
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: NTrent Piepho <tpiepho@freescale.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NJon Loeliger <jdl@freescale.com>
-
由 Trent Piepho 提交于
The local bus clock divider should be doubled for both 8610 and 8641. Signed-off-by: NTrent Piepho <tpiepho@freescale.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NJon Loeliger <jdl@freescale.com>
-
由 Trent Piepho 提交于
The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: NTrent Piepho <tpiepho@freescale.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NJon Loeliger <jdl@freescale.com>
-
由 Dave Liu 提交于
If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: NDave Liu <daveliu@freescale.com>
-
由 Paul Gortmaker 提交于
The values given for the PHY address were wrong, so the code read no valid PHY ID, and fell through to the generic PHY support, which would work on 1000M but would not auto negotiate down to 100M or 10M. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
-
由 Paul Gortmaker 提交于
Lets make things a bit more user friendly. It isn't 1985 anymore. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
-
由 Paul Gortmaker 提交于
These interfaces don't have usable connectors on the board, so don't bother enumerating or configuring them. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
-