- 09 8月, 2012 1 次提交
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由 Matthew McClintock 提交于
Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: NJiang Yutang <b14898@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 01 8月, 2012 1 次提交
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由 Gerlando Falauto 提交于
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need to keep them as separate .h config files. Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h file. Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
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- 10 7月, 2012 1 次提交
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由 Thierry Reding 提交于
The Tamonten Evaluation Carrier is an evaluation board for the Tamonten processor board. More information is available here: http://www.avionic-design.de/en/products/nvidia-tegra-tamonten-system-en/nvidia-tegra-tamonten-evboard-en.htmlSigned-off-by: NThierry Reding <thierry.reding@avionic-design.de> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 07 7月, 2012 14 次提交
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由 esw@bus-elektronik.de 提交于
* add support for board VL+MA2SC * adds vl_ma2sc_config for standard NOR boot configuration * adds vl_ma2sc_ram_config for RAM load configuration Signed-off-by: NJens Scharsig <esw@bus-elektronik.de>
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由 Vipin KUMAR 提交于
This patch adds options for all the below mentioned configurations and subsequently renames the include/configs/spearxxx.h files to spear3xx_evb.h, spear6xx_evb.h etc to depict evaluation board configuration. SPEAr3xx and SPEAr6xx boards can be compiled in following configurations 1. Environment placed in NAND 2. Console on usb device 3. Console on usb device with environment placed in NAND 4. SPEAr310 and SPEAr320 support environment variables in parallel NOR flash. Signed-off-by: NVipin Kumar <vipin.kumar@st.com> Signed-off-by: NAmit Virdi <amit.virdi@st.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Holger Brunck 提交于
Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Valentin Longchamp 提交于
This adds a first support of the FPGA download for a PCIe FPGA based on the BOCO2 CPLD. This takes place in 3 steps, all done accessing the SPICTRL reg of the BOCO2: 1) start the FPGA config with an access to the FPGA_PROG bit 2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1 for the end of the FPGA configuration (with a timeout) 3) reset the FPGA 4) finally remove the access to its config EEPROM from the FPGA so that the CPU can update the FPGA configuration when the kernel is running The boards with a PCIe FPGA but without BOCO2 still are supported. The config option name is CONFIG_KM_FPGA_CONFIG Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Holger Brunck 提交于
The additional headerfile is unneeded here, we can use the generic km_kirkwood.h instead. And we can use the better config option KM_PIGGY4_88E6061 for the specific features for boards with this design in km_arm.c. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Holger Brunck 提交于
Use the generic header km_kirkwood.h and get rid of the board specific header. changes for v2: rebased because of changes in other patches Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Holger Brunck 提交于
For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Holger Brunck 提交于
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have. Some other details: - IVM EEPROM is at adress: pca9547:70:9 - PCI is enabled - PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Wolfgang Denk <wd@denx.de>
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由 Michael Walle 提交于
This patch adds support for both the Linkstation Live (LS-CHLv2) and Linkstation Pro (LS-XHL) by Buffalo. Signed-off-by: NMichael Walle <michael@walle.cc> Cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Holger Brunck 提交于
Some other kirkwood boards from keymile will follow. They will have some small differences, but we want to use the km_kirkwood.h for all to distinguish them. This patch a preparation for this. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Whistler is a highly configurable Tegra evaluation and development board. This change adds support for the following specific configuration: E1120 motherboard E1108 CPU board E1116 PMU board The motherboard configuration switches are set as follows: SW1=0 SW2=0 SW3=5 S1/S2/S3/S4 all on, except S3 7/8 are off. Other combinations of daugher boards may work to varying degrees, but will likely require some SW adjustment. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Prabhakar Kushwaha 提交于
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC is an integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements BSC9131RDB Overview ----------------- -1Gbyte DDR3 (on board DDR) -128Mbyte 2K page size NAND Flash -256 Kbit M24256 I2C EEPROM -128 Mbit SPI Flash memory -USB-ULPI -eTSEC1: Connected to RGMII PHY -eTSEC2: Connected to RGMII PHY -DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NAkhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: NRajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
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- 16 6月, 2012 2 次提交
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由 Holger Brunck 提交于
This board is a MPC8360 board. Two flashes are present a NOR flash were u-boot and the u-boot environment is stored and a NAND flash for the application code. This board has 512MB SDRAM. Additionaly we introduce a common km8360.h file and convert kmeter1 to use this. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> Signed-off-by: NChristian Herzig <christian.herzig@keymile.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Heiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Holger Brunck 提交于
This additional header is unneeded, we can use the tuxx1.h for this target. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Heiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 28 5月, 2012 3 次提交
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由 Phil Edworthy 提交于
This is an sh2a device (max 266MHz) with FPU, video display controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports, SD and on-chip USB. The RSK2+SH7269 board uses the SH7269 processor. It is often referred to as just rsk7269. Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Nobuhiro Iwamatsu 提交于
The AP-SH4A-4A board has SH7734, 64MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 64MB DDR2-SDRAM - 16MB NOR Flash memory - Serial console (SCIF) - Ethernet (SH-Ether with Gigabit) - I2C Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Nobuhiro Iwamatsu 提交于
The r0p7734 board has SH7734, 128MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 128MB DDR2-SDRAM - 32MB NOR Flash memory - Serial console (SCIF) - Ethernet (SH-Ether/SMSC) Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 15 5月, 2012 5 次提交
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由 Stefano Babic 提交于
The ESG ima3-mx53 board is based on the Freescale i.MX53 SOC. It boots from NOR (128 MB) and supports Ethernet (FEC), SATA. Signed-off-by: NStefano Babic <sbabic@denx.de>
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由 Enric Balletbò i Serra 提交于
This is rework on config files of IGEP-based boards with the aim to remove duplicated code to be more maintainable. Basically this patch creates a common configuration file for both boards and only sets the specific option in the board config file. On board files the hardcored mach type was replaced in favour of using the CONFIG_MACH_TYPE option. More than 200 duplicated lines have been deleted. Signed-off-by: NEnric Balletbo i Serra <eballetbo@gmail.com>
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由 David Purdy 提交于
This patch adds support for Cloud Engines Pogoplug E02 Information regarding the CE Pogoplug E02 board can be found at: http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgraySigned-off-by: NDave Purdy <david.c.purdy@gmail.com> Cc: prafulla@marvell.com Cc: albert.u.boot@aribaud.net
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由 Luka Perkov 提交于
Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. NAS6210 has 1 SATA and 1 eSATA port while NAS6220 has 2 SATA ports. More information about the boards can be found here: http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036 http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515Signed-off-by: NLuka Perkov <uboot@lukaperkov.net> Signed-off-by: NGerald Kerma <dreagle@doukki.net> Signed-off-by: NSimon Baatz <gmbnomis@gmail.com>
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由 Vladimir Zapolskiy 提交于
This change adds a basic support for Embest/Timll DevKit3250 board, NOR and UART are the only supported peripherals for a moment. The board doesn't require low-level init, because the initial SDRAM and GPIO configuration is performed during kickstart bootloader execution. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: NMarek Vasut <marek.vasut@gmail.com>
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- 30 4月, 2012 1 次提交
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由 Dirk Eibach 提交于
In order to add boards that have different hardware for fpga reset, any 405ep gdsys board now provides these functions: void gd405ep_init(void); void gd405ep_set_fpga_reset(unsigned state); void gd405ep_setup_hw(void); int gd405ep_get_fpga_done(unsigned fpga); Signed-off-by: NDirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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- 25 4月, 2012 3 次提交
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由 Liu Gang 提交于
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
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由 Liu Gang 提交于
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
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由 Shaohui Xie 提交于
New P2041RDB board will add a NAND chip, so add support for NAND and NAND boot. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 22 4月, 2012 1 次提交
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由 Macpaul Lin 提交于
board: Add config file of board adp-ag102 Add adp-ag102 into boards.cfg Add adp-ag102 into MAINTAINERS doc: add README of ag102 Signed-off-by: NMacpaul Lin <macpaul@andestech.com>
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- 02 4月, 2012 1 次提交
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由 Daniel Schwierzeck 提交于
Make endianess of target CPU configurable. Use the new config option for dbau1550_el and pb1000 boards. Adapt linking of standalone applications to pass through endianess options to LD. Build tested with: - ELDK 4 mips_4KC- and mips4KCle - Sourcery CodeBench Lite 2011.03-93 With this patch all 26 MIPS boards can be compiled now in one step by running "MAKEALL -a mips". Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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- 29 3月, 2012 1 次提交
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由 Tom Rini 提交于
The CS_AUTOBOOT configurations have been broken for a long time. Kshitij Gupta is no longer at TI making these broken and orphaned boards, so remove. Signed-off-by: NTom Rini <trini@ti.com>
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- 27 3月, 2012 1 次提交
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de>
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- 28 2月, 2012 3 次提交
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In commit 2d575e46 a separate header file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h. The substantial difference between the davinci_dm6467evm and the davinci_dm6467Tevm configuration is a single bit in the hardware revision that is passed to the Linux kernel and davinci_dm6467evm has REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a REFCLK_FREQ = 33000000. This patch removes include/configs/davinci_dm6467Tevm.h. Instead the include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined in boards.cfg. Signed-off-by: NPrabhakar Lad <prabhakar.csengg@gmail.com> Cc: Tom Rini <trini@ti.com>
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由 Hadli, Manjunath 提交于
add support to read mac address for AM18x EVM manufactured from Spectrum digital which have mac address stored in I2C EEPROM manufactured by WINBOND. This patch reads mac address from I2C EEPROM and sets the environment variable if not set, If mac address is already present in environment compare it with the mac address in EEPROM and warn on mismatch.Introduced a config option CONFIG_MAC_ADDR_IN_EEPROM to where to look for the mac address. Signed-off-by: NManjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Wolfgang Denk <wd@denx.de>
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由 Hadli, Manjunath 提交于
add support to read mac address for da850/L138 evm manufactured by Logic PD which store mac address in SPI flash manufactured by ST Microelectronics. This patch adds support to read mac address from SPI flash and set the mac address if it hasn't been set in environment, If it has been set in the environment it compares the value one with SPI flash and warns on mismatch. Introduced a config option CONFIG_MAC_ADDR_IN_SPIFLASH indicating where to look mac address for. Signed-off-by: NManjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Wolfgang Denk <wd@denx.de>
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- 13 2月, 2012 2 次提交
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由 Dimitar Penev 提交于
This adds support for the BR4 Appliance. It is a quad channel ISDN BRI board based on Blackfin BF537 CPU. Signed-off-by: NDimitar Penev <dpn@switchfin.org> Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Dimitar Penev 提交于
This add support for the PR1 Appliance - Asterisk based ISDN PRI PBX. This board is Blackfin BF537 based. The schematics are not fully opened. Signed-off-by: NDimitar Penev <dpn@switchfin.org> Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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