- 05 5月, 2015 6 次提交
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由 Minghuan Lian 提交于
Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> [York Sun: Fix T4240RDB_SDCARD_defcofig] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Scott Wood 提交于
Commit 96d2bb95 ("powerpc/mpc85xx: Don't relocate exception vectors") simplified IVOR initialization a bit too much, failing to use the post-relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes: 96d2bb95 ("powerpc/mpc85xx: Don't relocate exception vectors") Signed-off-by: NScott Wood <scottwood@freescale.com> Cc: Alexander Graf <agraf@suse.de> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Tested-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 29 4月, 2015 29 次提交
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Masahiro Yamada 提交于
Move arch/arm/include/asm/arch-zynq/* -> arch/arm/mach-zynq/include/mach/* Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Masahiro Yamada 提交于
Move arch/arm/cpu/armv7/zynq/* -> arch/arm/mach-zynq/* Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Masahiro Yamada 提交于
The comment line in arch/arm/cpu/armv7/zynq/config.mk says that the option "-mfpu=neon" is necessary for compiling lowlevel_init.S. We do not have to give it to all the source files. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Enable SDHCI0 for zynqmp. Add empty gpio.h because of sdhci requirement. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Provide an option to write filesystem independend commands. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Added the SPI driver support for ZynqMP The controller is same as zynq SPI controller Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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Enable the i2c driver for ZynqMP Also enable the eeprom for read and writes to eeprom on ZynqMP ZynqMP uses the same i2c controller as in Zynq Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add support for EMMC bootmode. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Fix wrong timer calculation in get_timer_masked incase of overflow. This fixes the issue of getting wrong time from get_timer() calls. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Remove the quirk SDHCI_QUIRK_NO_CD as it is not required. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
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Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Disable all level shifters before enabling the PS-to-PL level shifters as it would be good to disable all level shifters before enabling the PS-to-PL in order to ensure that it is in proper state Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Masahiro Yamada 提交于
We are about to change the location for ps7_init files, breaking the current work-flows. It is good time to drop the legacy ps7_init.c/h support. Going forward, please use ps7_init_gpl.c/h all the time. If you are still using old Xilinx tools that are only able to generate ps7_init.c/h, rename them into ps7_init_gpl.c/h. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: NSören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
The PicoZed is a System-on-Module board which is marketed as part of the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000 processor. This patch adds support that covers all the variants of the PicoZed including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This patch set however only covers support for the System-on-Module and does not cover any extra components that are available on carrier boards (except those that are fanned out of the module itself). More information on this board, its variants and available carrier boards is available at: http://zedboard.org/product/picozedSigned-off-by: NNathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
On slow platforms not all baudrate setting is valid. Check it directly in the driver and setup maximum possible frequency. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Enable GPIO driver and GPIO commands. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Andrea Scian 提交于
Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: NAndrea Scian <andrea.scian@dave.eu> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
It is possible for CONFIG_XILINX_EMACLITE to be defined without XILINX_EMACLITE_BASEADDR being defined as the EMAC Lite driver support OF init. Check that the driver is enabled and the base address is available before initializing with a static base address. Signed-off-by: NNathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Simon Glass 提交于
These functions now rely on uclass_find_first/next_device() and assume that they will either return failure (-ve error code) or a device. In fact, coming to the end of a list is not considered failure and they return 0 in that case. The logic to deal with this was replaced in commit acb9ca2a with just using uclass_get_device_tail(). Add back the missing logic. This bug was caught by unit tests but since they were broken for other reasons at the time, this was not noticed. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Axel Lin 提交于
This was accidentally added by commit dd0b0122 "serial: ns16550: Add an option to specify the debug UART register shift". Remove it. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
Trivial bug fix for commit 5a87c417 (dm: core: Drop device removal error path when not supported). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 28 4月, 2015 4 次提交
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Upto now flash sector_size is assigned from params which isn't necessarily a sector size from vendor, so based on the SECT_* flags from flash_params the erase_size will compute and it will become the sector_size finally. Bug report (from Bin Meng): => sf probe SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB, total 2 MiB, mapped at ffe00000 => sf erase 0 +100 SF: 65536 bytes @ 0x0 Erased: OK Signed-off-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reported-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
With SPI flash moving to driver model, commit fbb09918 "dm: Convert spi_flash_probe() and 'sf probe' to use driver model" ignored the SST flash-specific write op (byte program & word program), which actually broke the SST flash from wroking. This commit makes SST flash work again under driver model, by adding SST flash-specific handling in the spi_flash_std_write(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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由 Bin Meng 提交于
Add a new member 'flags' in struct spi_flash to store the flash flags during spi_flash_validate_params(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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- 27 4月, 2015 1 次提交
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由 David Dueck 提交于
The timeout value is never reset during the transfer. This means that when transferring more data we eventually trigger the timeout. This was reported on the mailing list: "Spansion SPI flash read timeout with AM335x" Signed-off-by: NDavid Dueck <davidcdueck@googlemail.com> CC: Tom Rini <trini@konsulko.com> CC: Stefan Roese <sr@denx.de> CC: Andy Pont <andy.pont@sdcsystems.com> Tested-by: NDavid Dueck <davidcdueck@googlemail.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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