- 08 10月, 2020 28 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-mips由 Tom Rini 提交于
- mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
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由 Stefan Roese 提交于
Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: NStefan Roese <sr@denx.de> Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Aaron Williams 提交于
This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This patch adds the coremask handling functions. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
Add header to handle Octeon fuse access. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This header includes common register defines and accessor functions. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch enables USB support with some helpful commands, like fs support. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds the glue layer for the MIPS Octeon SoCs. It's ported mainly from the Linux code. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
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由 Stefan Roese 提交于
Octeon uses mapped addresses for virtual and physical memory. It's not that easy to calculate the resulting addresses here. So let's remove this BUG_ON() completely, as it's not really helpful. Please also note, that BUG_ON() is not recommended any more in the Linux kernel. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
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由 Stefan Roese 提交于
On MIPS platforms, mapping of the base address is needed. This patch switches from dev_get_addr() to dev_remap_addr() to get the mapped base address of the xHCI controller. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
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由 Stefan Roese 提交于
This patch adds the board specific configuration (struct) for the Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium / Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in the board defconfig for its usage. Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB). Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 2 includes the very complex Octeon 3 DDR4 configuration Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 1 adds the base U-Boot RAM driver, which will be instantiated by the DT based probing. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi file. It also adds the L2C DT node, as this is referenced by the DDR driver. Signed-off-by: NStefan Roese <sr@denx.de>
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- 07 10月, 2020 1 次提交
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git://git.denx.de/u-boot-dm由 Tom Rini 提交于
bloblist enhancement for alignment Update ofnode/dev_read phandle function sandbox keyboard enhancements and fixes
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- 06 10月, 2020 11 次提交
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由 Heinrich Schuchardt 提交于
When using SDL for input the SDL key codes are first converted to Linux key codes and then to matrix entries of the cross wired keyboard. We must not map any key code to two different places on the keyboard. So comment out one backslash position. Update the rest of the file from Linux 5.7. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Heinrich Schuchardt 提交于
Add missing SDL key scan codes, e.g. * shift, ctrl, meta, alt * brace/bracket Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Add unitary test for phandle access functions - ofnode_count_phandle_with_args - ofnode_parse_phandle_with_args - dev_count_phandle_with_args - dev_read_phandle_with_args Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
The result of fdt_node_offset_by_phandle is negative for error, so this patch corrects the check of this result in fdtdec_parse_phandle_with_args. This patch allows to have the same behavior with or without OF_LIVE for the function dev_read_phandle_with_args with cell_name = NULL and with invalid phandle. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Update the test for node.of_offset because an invalid offset is not always set to -1 because the return value of the libfdt functions are: + an error with a value < 0 + a valid offset with value >=0 For example, in ofnode_get_by_phandle() function, we have: node.of_offset = fdt_node_offset_by_phandle(gd->fdt_blob, phandle); and this function can return -FDT_ERR_BADPHANDLE (-6). Without this patch, the added test dm_test_ofnode_get_by_phandle failed. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Stefan Roese 提交于
Include missing log.h and change _ofnode_to_np() to ofnode_to_np() so that compiling with OF_CHECKS enabled does not break. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Adjust a few comments to make the meaning clearer. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Some blobs need a larger alignment than the default. For example, ACPI tables often start at a 4KB boundary. Add support for this. Update the size of the test blob to allow these larger records. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The intention which bloblists is that each blob's data is aligned in memory. At present it is only the headers that are aligned. Update the code to correct this and add a little more documentation. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
When running these tests on sandbox any failures result in very large or long pointer values which are a pain to work with. Map them to an address so it is easier to diagnose failures. Signed-off-by: NSimon Glass <sjg@chromium.org>
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