- 14 4月, 2018 3 次提交
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由 Peng Fan 提交于
No need to provide two prototype for this function. Use ulong for the first parameter, then this function could be shared for DM/non DM case. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Ye Li 提交于
When using ethernet DM driver, the recv interface has a change with non-DM interface, that driver needs to set the packet pointer and provide it to upper layer to process. In fec driver, the fecmxc_recv functions does not handle the packet pointer parameter. This may cause crash in upper layer processing because the packet pointer is not set. This patch allocates a buffer for the packet pointer and free it through free_pkt interface. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Matt Pelland 提交于
mvneta already supports setting the MAC address but this was only done internally when some other part of U-Boot tries to actually use the interface. This commit exposes this functionality to the ethernet core code so that the MAC addresses of all interfaces are configured correctly even if they are not used before loading Linux. Signed-off-by: NMatt Pelland <mpelland@starry.com> Reviewed-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 13 4月, 2018 2 次提交
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- 12 4月, 2018 35 次提交
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由 Marek Vasut 提交于
The Gen3 kernel images are often above 8 MiB, increase the maximum kernel size to 64 MiB to future-proof it, just like many other ARM64 boards do. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Fix up the memory map on Gen3 to match datasheet properly. This simplifies the memory map setup as well, since we do no longer need this massive complexity. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing the SPI transmission 1 byte at time, if there is a 32byte chunk of data to be transferred, fill the FIFO completely and then transfer the data to/from the FIFO. This increases the SPI NOR access speed significantly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Replace the ad-hoc endless loops with wait_for_bit() with reasonable timeout. Note that the loops had internal 10uS delays, although there is no reason for those on this HW, so they are dropped. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Waiting for SPBDCR == 1 is not required and is covered by the subsequent wait for SPSR_SPRFF, so drop this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Just replace unsigned {char,short,long} with u{8,16,32}, no functional change. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Marek Vasut 提交于
Add driver for the RPC block in SPI-flash mode. This driver allows access to a SPI NOR flash attached to the RPC block and does not support RPC in Hyperflash mode. Note that this block is extremely selective when communicating with the SPI NOR. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add driver for the RPC block in Hyperflash mode. This driver allows access to a CFI Hyperflash attached to the RPC block and does not support RPC in SPI mode. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
The IP requires some time to recuperate after the IO pin properties were changed. Add a delay to assure this. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Fix minor rebase omission, the else was missing which triggered two accesses to the register on 64bit variant of the IP. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The HOST_MODE register must be set to 0 when the IP is operated in 16bit mode, otherwise 16bit access to the data FIFO may fail. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
There are only a few registerse used in the 16bit mode which are 32bit internally. Special-case only those in the IO accessors and always write both halves. Any other register access is protected from accidentally overwriting neighboring register. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Enable the HS200 on RCar Gen3 platforms, since the SDHI core supports it. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Export the matsu_sd_{read,write}l() common register access functions, so that they can be used by other drivers sharing the common code. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Handle bus width 0 as 1-bit bus to assure valid content of MATSU_SD_OPTION register WIDTH field. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Drop the ad-hoc DT caps parsing in favor of common framework function. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants of the IP. There is no DT property which allows discerning those, so what Linux does is it checks the size of the register area and if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle the distinction the same way. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Certain instances of the SD IP require more elaborate digging in the DT to figure out which variant of the SD IP is in use. Allow explicit passing of the quirks into the probe function. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add support for 16bit mutation of the Matsushita SD IP. Since some registers are internally 32bit, the matsu_sd_{read,write}l() has to special-case this 16bit variant a bit. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Drop useless check in matsu_sd_{read,write}q(), this is only ever called to read the data from FIFO and only when 64bit variant of the block is used anyway. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add macros to generate the FIFO accessors, since the code is almost the same with only minor differences. This is done in preparation for adding 16bit variant of the IP. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Since the Renesas SDHI has it's own custom driver sharing the common code with Uniphier one, adjust the Kconfig entries. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add Kconfig entry for the Renesas SDHI variant of the controller and split the Makefile entries accordingly. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Factor out common code from the uniphier SD driver, change the prefix of the functions from uniphier_sd_ to matsu_sd_ and create separate renesas-sdhi.c driver. Thus far, all the code is still compiled when CONFIG_UNIPHIER_MMC is selected and there is no functional change. This patch is a preparation for further split of the SoC specific parts of the Matsushita SD driver, used both on Uniphier and R-Car. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Enable the HUSH shell, since it is far more capable. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add JTAG recovery support into the M2 Porter TPL. This allows the TPL to be loaded over JTAG, initialize the system, wait for the JTAG debugger to load U-Boot image into RAM and then resume and start U-Boot from RAM. The procedure is as follows: 1) Load u-boot-tpl.bin to 0xe6300000 2) Write magic number 0x1337c0de to 0xe6300020 TPL checks for this particular magic and starts JTAG recovery if this number is present. This is not present by default. 3) Start U-Boot TPL from 0xe6300000 4) Wait for a message from TPL on UART indicating JTAG boot: "JTAG boot detected!" 5) Halt the system in JTAG debugger 6) Load U-Boot image (u-boot.img) to 0x4fffffc0 7) Write magic number 0xb33fc0de to 0xe6300024 TPL checks for this particular magic to verify that the U-Boot image was loaded into DRAM by the JTAG debugger. 8) Resume the system in JTAG debugger Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add and enable TPL on M2 Porter. The TPL must fit into 16 kiB due to the Gen2 BootROM restriction. The TPL is running from MERAM and is capable of performing the initial initialization of PFC, Clock, GPIO, LBSC, DBSC and QSPI NOR. DBSC is responsible for bringing up the DDR DRAM access. The TPL is capable of loading the next stage, U-Boot, from either SPI NOR or UART as a fallback. If either does provide a valid U-Boot uImage, the system stops, which allows the operator to load U-Boot ie. via JTAG and start it manually. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Skip the cache initialization, which can be done later on in U-Boot proper, since this interferes with early DRAM initialization in TPL. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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