- 03 6月, 2013 4 次提交
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由 Tom Wai-Hong Tam 提交于
This patch does a similar code reogranzation from http://patchwork.ozlabs.org/patch/132179/ which is based on an old version of code (fdt support and bus selection still not in). It merges this tidy-up on top of the recent code. It does not make any logical change. tpm.c implements the interface defined in tpm.h based on underlying LPC or I2C TPM driver. tpm.c and the underlying driver communicate throught tpm_private.h. Note: Merging the LPC driver with tpm.c is left to future patches. Change-Id: Ie1384f5f9e3935d3bc9a44adf8de80c5a70a5f2b Signed-off-by: NTom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Vincent Palatin 提交于
Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs, which supports clockstretching, combined reads and a bus speed of up to 400khz. The device also has a new device id. This is based on the kernel patch provided by Infineon : https://gerrit.chromium.org/gerrit/42332Signed-off-by: NVincent Palatin <vpalatin@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NLuigi Semenzato <semenzato@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NVincent Palatin <vpalatin@chromium.org> Tested-by: NTom Wai-Hong Tam <waihong@chromium.org> Tested-by: NVincent Palatin <vpalatin@chromium.org>
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由 Tom Wai-Hong Tam 提交于
The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: NTom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Che-liang Chiou 提交于
The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: NPeter Huewe <peter.huewe@infineon.com> Signed-off-by: NChe-Liang Chiou <clchiou@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NMike Frysinger <vapier@gentoo.org> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NTom Wai-Hong Tam <waihong@chromium.org>
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- 01 6月, 2013 2 次提交
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由 Sergey Lapin 提交于
This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: NSergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 31 5月, 2013 4 次提交
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由 Albert ARIBAUD 提交于
Replace all relocate_code routines from ARM start.S files with a single instance in file arch/arm/lib/relocate.S. For PXA, this requires moving the dcache unlocking code from within relocate_code into c_runtime_cpu_setup. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: NSimon Glass <sjg@chromium.org>
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- 30 5月, 2013 1 次提交
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由 Albert ARIBAUD 提交于
Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
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- 29 5月, 2013 8 次提交
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由 Axel Lin 提交于
Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Tested-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Axel Lin 提交于
cpu_init_crit() can be skipped, but the code is still enabled requiring a platform to supply lowlevel_init(). Signed-off-by: NAxel Lin <axel.lin@ingics.com> Tested-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically to any other Tegra20. My Whistler board has a SoC with this SKU. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically to any other Tegra114. This value is used on (at least some) Dalmore boards with a production rather than engineering chip. Such boards are in the hands of some partners who want to use upstream U-Boot. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Even when eventually building u-boot-dtb-tegra.bin, separately building u-boot-nodtb-tegra.bin can be useful, since building it encapsulates the SPL padding step. If you want to tweak u-boot.dtb and regenerate u-boot-dtb-tegra.bin, it is then a simple cat operation. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Allen Martin 提交于
When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like "sf" where the user can pass a clock speed on the command line or "sspi" where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: NAllen Martin <amartin@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
Tegra builds use the common u-boot-spl.lds now. Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
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由 Tom Warren 提交于
Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both board and board_name == beaver. Didn't test as I have no T30 Beaver board here. Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com>
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- 25 5月, 2013 21 次提交
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由 York Sun 提交于
dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ruchika Gupta 提交于
Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Acked-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaveta Leekha 提交于
Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in eth port enum structure, it will assign mdio mux depend on this assumption. This is not true with Fman V3, which added more 1G ports after port DTSEC5 in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux. So we use dynamic index for 10G ports instead of hardcoded enum value when doing mdio mux for 10G ports. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Poonam Aggrwal 提交于
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Xie Xiaobo 提交于
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters. Signed-off-by: NXie Xiaobo <X.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaveta Leekha 提交于
Crossbar switches were wrongly programmed to route the CPRI lanes to SFP as the connectivity table was not correct. Modified it correctly for SFPs connections. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shengzhou Liu 提交于
QSGMII card has different PHY address against previous SGMII card. We check the type of card in slots and set correct PHY address to avoid complainning "PHY reset timed out" during u-boot booting up. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Suresh Gupta 提交于
- Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen George 提交于
Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: NStephen George <stephen.george@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ed Swarthout 提交于
Use QIXIS measurement registers to obtain sysclk and ddr clock. This allows using non-standard clock speeds, set by directly writing to clock chip or store the values in qixis clock data eeprom. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ed Swarthout 提交于
QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 James Yang 提交于
This is compile-time config. Signed-off-by: NJames Yang <James.Yang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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