Current driver assumes the AHCI is connected to PCI, this is not
true on some SoCs, e.g. LS1021A, which has PCI but the AHCI is
in SoC. This patch will enable embedded AHCI devices on platforms
with PCI.
PCI AHCI devices still can be used by commenting CONFIG_SCSI_AHCI_PLAT
option in head file.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NKamil Lulko <rev13@wp.pl>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NKamil Lulko <rev13@wp.pl>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NKamil Lulko <rev13@wp.pl>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NKamil Lulko <rev13@wp.pl>

Add gzwrite command to write gzip-compressed images to block devices.

Input must be gzip-compressed according to RFC1952, since the crc
and file size in the trailer will be confirmed during operation.
The decompressed file size must be specified on the command line
for images with decompressed sizes >= 4GiB because the trailer
only contains the low 32 bits of the original file size.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>

Initial filesystem images are generally highly compressible.

Add a routine gzwrite that allows gzip-compressed images to be
written to block devices.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: NTom Rini <trini@ti.com>

commit aed2fbef
"dm: serial: Tidy up the pl01x driver"
caused a regression on (real hardware) PL010 by omitting
to update the line control register when switching baudrate.

Fix this by inlining the missing write to the baud control
register.

Also renaming the set_line_control() function to
pl011_set_line_control() since this function is clearly
PL011-specific, and it won't suffice to call that to
set up line control.

Tested on the Integrator/AP hardware.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

two CMD_DNS options were added by commit 60296a83 ("commands: add more
command entries in Kconfig")
Signed-off-by: NAndrey Skvortsov <andrej.skvortzov@gmail.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The name "pch_gbe.%x" exceeds the limit of the name in the
'struct eth_device'. Rename it as just "pch_gbe".
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Use phys_addr_t which is used in function prototype
in system.h.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

commit 3c6928fd "net: phy: fix warnings with W=1" caused
some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the
warning and make those special PHYs working as well.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>

This patch adds a support for KSZ8081MNX in MII mode.
Signed-off-by: NLuca Ellero <luca.ellero@brickedbrain.com>
Acked-by: NPavel Machek <pavel@denx.de>

When accessing PHY registers it is often desirable to only update
selected bits, so it is necessary to first read the current value
before writing back an modified value with the relevant bits
updated.

To simplify this and to allow such operations to be incorporated
into simple shell scripts propose adding a 'modify' option to the
existing mii command, which takes a mask indicating the bits to
be updated in addition to a data value containing the new bits,
ie, <updated> = (<data> & <mask>) | (<current> & ~<mask>).
Signed-off-by: NTim <tim.james@macltd.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tim <tim.james@macltd.com>

Update to my corporate email and make the supported filter and aliases
more accurate.
Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>

Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
While at it, fix a couple of pointer to integer cast size mismatch
warnings by casting through unsigned long going from pointers to
integers and vice versa.

Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have
interrupts enabled by default. If the interrupt is not treated later by
the OS and the PHY's interrupt line is enabled and shared with other
interrupts, the system will get an interrupt storm. This patch disables
the interrupt for PHY devices that use one of the current Realtek
Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L)
have the interrupt masked. In this case, the functionality of the PHY
should not be afected since this patch brings INER and INSR registers to
their default values.
Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

U-Boot on this board grew a long time ago past the 384 KiB that
it reserves for the U-Boot image, before the environment.  Thus,
saveenv overwrites the U-Boot image and bricks the board.

I tried to find out when U-Boot grew beyond this point, but there is a
long stretch in the history where this board did not build -- and
AFAICT when it did fit in 384 KiB, it was missing vital features such
as fdt support.  Turning off CONFIG_VIDEO was not enough to make it
fit.  Thus, I don't think we have any choice other than to move the
environment.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

CONFIG_PHY_AQ1202 is no longer needed, use CONFIG_PHY_AQUANTIA.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

U-Boot does not have system calls (the services it exposes to
standalone commands use a different mechanism), so the syscall handler
is dead code.  It's also broken code, as it assumes it is located at
0xc00 -- while even before the patch to stop relocating exception
vectors to 0, U-Boot had the syscall at 0x900.

The critical and machine check return paths are never called -- the
regular exception return path is used instead, which works because
xSRR0/1 have already been saved and can be restored via the regular
SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck
inside another exception prolog/epilog).

Also remove a few other small unused functions.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Booke does not require exception vectors to be located at address zero.
U-Boot was doing so anyway, simply because that's how it had been done
on other PPC.  The downside of this is that once the OS is loaded to
address zero, the exception vectors have been overwritten -- which
makes it difficult to diagnose a crash that happens after that point.

The IVOR setup and trap entry code is simplified somewhat as a result.

Also, there is no longer a need to align individual exceptions on 0x100
byte boundaries.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB.
Enable CONFIG_CMD_MEMTEST as well.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR
to define that firmware of cortina driver is stored in the
nor flash.
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.
Signed-off-by: NYing Zhang <b40530@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T2080 rev1.1 also needs erratum a007186.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine
to reside in higher address space.

Unfortunately, this exposed a glitch in u-boot for ppce500: While providing
a function to dynamically evaluate the CCSR region's position in physical
address space, we never used it. Plus we forgot to support 64bit physical
addresses.

This patch fixes that mishap, making u-boot work fine with latest QEMU again.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.

>From section 9.4.1.8 of that manual:

   Source synchronous enable. This bit field must be set during
   initialization. See Section 9.6.1, "DDR SDRAM Initialization
   Sequence," details.

   0 - Reserved
   1 - The address and command are sent to the DDR SDRAMs source
       synchronously.

In addition, Freescale application note AN2805 is also very clear that
this bit must be set.

This patch reverts a change introduced by commit
457caecd.

Testing Done:

Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set.  There is one extra instruction emitted:

  fff9b774: 65 29 80 00  oris    r9,r9,32768

Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.

Booted an image on a MPC8541 based board successfully.
Signed-off-by: NCurt Brune <curt@cumulusnetworks.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NHeiko Schocher <hs@denx.de>

the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.

This should be removed, if a clock framework is availiable.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Tested-by: NEric Nelson <eric.nelson@boundarydevices.com>

make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always 650000000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Tested-by: NEric Nelson <eric.nelson@boundarydevices.com>

Make the sandbox setup more generic/examplary by including
config_distro_defaults.h and config_distro_bootcmd.h.

Among other things this makes it easy to test whether images will boot
though with the standard distro bootcmds by running e.g:
  u-boot -c 'host bind 0 myimage.img ; boot'

By default there are 2 target host devices to emulate device with
multiple storage devices (e.g. internal ("host 0") and external
("host 1") and verify that the prioritization and fallbacks do work
correctly.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed by: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Define default PXE client architecture identifiers for IA32 (0x0 aka
Intel x86PC) and Intel x86-64 (0x9 aka EFI x86-64).

This prepares for usage for config_distro_defaults in the sandbox
architecture
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>

Properly map memory through map_sysmem so that pxe can be used from the
sandbox.

Tested in sandbox as well as on jetson-tk1, odroid-xu3, snow as peach-pi
boards
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

Define the common shared block environment for the host interface in
preperation for the sandbox build to use config_distro_bootcmd.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>

A common pattern to check if a certain device exists (e.g. in
config_distro_bootcmd) is to use: <interface> dev [device]

Implement host dev [device] so this pattern can be used for sandbox host
devices.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

As suggested by Simon Glass, rename the sb command to host but keep the
old sb command as an alias
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

Add dummy bootz_setup implementation allowing the u-boot sandbox to
run bootz. This recognizes both ARM and x86 zImages to validate a
valid zImage was loaded.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>