- 26 8月, 2015 29 次提交
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由 Masahiro Yamada 提交于
This allows Patman to generate smaller patches for file removal. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Bin Meng 提交于
Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
It turns out that calling fsp_init_phase_pci() in arch_misc_init() is subject to break pci device drivers as with driver model, when the bus enumeration happens is not deterministic. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
With dm pci conversion, pci config read/write in unprotect_spi_flash() silently fails as at that time dm pci is not ready and bus enumeration is not done yet. Actually we don't need to do this in that early phase, hence we delay this call to arch_misc_init(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Add some comments in start.S for the fact that with FSP U-Boot actually enters the code twice. Also change to use fsp_init() and fsp_continue for accuracy. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
After fsp_init() returns, the stack has already been switched to a place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. Enlarge the size of malloc() pool before relocation since we have plenty of memory now. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Move x86_fsp_init() call after initf_malloc() so that we can fix up the gd->malloc_limit later. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
When ifdtool collates the microcode into one place it effectively creates a copy of the 'data' properties in the device tree microcode nodes. This is wasteful since we now have two copies of the microcode in the ROM. To avoid this, remove the microcode data from the device tree and shrink it down. This means that there is only one copy and the overall ROM space used by the microcode does not increase. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The Intel Firmware Support Package (FSP) requires that microcode be provided very early before the device tree can be scanned. We already support adding a pointer to the microcode data in a place where early init code can access. However this just points into the device tree and can only point to a single lot of microcode. For boards which may have different CPU types we must support multiple microcodes and pass all of them to the FSP in one place. Enhance ifdtool to scan all the microcode, place it together in the ROM and update the microcode pointer to point there. This allows us to pass multiple microcode blocks to the FSP using its existing API. Enable the flag in the Makefile so that this feature is used by default for all boards. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The code to set up the microcode pointer in the ROM shares almost nothing with the write_uboot() function. Move it into its own function so it will be easier to extend. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Since U-Boot and its device tree can grow we should check that it does not overlap the regions above it. Track the ROM offset that U-Boot reaches and check that other regions (written after U-Boot) do not interfere. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
This commit adds the microcode blob for BayTrail-I D0 stepping, CPUID signature 30679h. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is incorrect since we require the -m parameter to the microcode tool. Update the two examples to show this. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
The doc has a misleading 'make menuconfig' when building the EFI application and payload. Clarify this and also update information on test with QEMU. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Currenlty we only set up video framebuffer when VIDEO_VESA driver is used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we already saved VESA mode in the VIDEO_COREBOOT driver, now we can also set up video framebuffer for coreboot before loading Linux kernel. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
When booting as a coreboot payload, the framebuffer details are passed from coreboot via configuration tables. We save these information into vesa_mode_info structure for future use. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
It looks that x86 chipset always contains a host bridge at pci b.d.f 0.0.0, so enable this for all boards. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
When running U-Boot bare-metal, the cbfs command is useless. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
When booting as a coreboot payload, we don't need write any configuration tables as coreboot does that for us. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Instead of hiding each menu entries under "System tables" for EFI, hide the main menu completely. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Some platforms may have >=4GiB memory, so we need make U-Boot report such configuration correctly when booting as the coreboot payload. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Now that we have generic routine to calculate relocation address, remove the x86 specific one which is now only used by coreboot. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
coreboot has some extensions (type 6 & 16) to the E820 types. When we detect this, mark it as E820_RESERVED. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
With recent EFI support, the entry point address of coreboot payload was changed. Now we update the address to use _x86boot_start, which is the same one for EFI. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
commit 6497e37a "net: e1000: Support 64-bit physical address" causes compiler warnings on 32-bit U-Boot build below. drivers/net/e1000.c: In function 'e1000_configure_tx': drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default] drivers/net/e1000.c: In function 'e1000_configure_rx': drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default] This commit fixes the build warnings. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 25 8月, 2015 11 次提交
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由 Marcel Ziswiler 提交于
This is useful once Andrew's PXA I2C driver gets merged. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Add optional LCD support. Note that depending on the toolchain used one might have to drop some other features to stay within the 0x40000 size limit. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Add some more NOR flash details like size, bus width and lock/unlock time outs. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Looks like the define CONFIG_SYS_LCD_PXA_NO_L_BIAS is not used anywhere else throughout the U-Boot sources any more. Drop it. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Marcel Ziswiler 提交于
Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
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由 Andrew Ruder 提交于
This patch moves pxa to the common timer functions added in commit 8dfafdde - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: NAndrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
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