Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add common clock code for Renesas RCar Gen2 platforms.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add macros for the DIV6P1 clock type, which is used on Gen2
and optionally also on Gen3.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Pull code which is common for RCar Gen2 and RCar Gen3 into
separate source file. No functional change.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add Kconfig entries for each SoC clock table, so they can be
compiled in or out at build time. This can reduce the size of
the binary if desired.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

The Gen2 requires setting RMSTPCR before booting, while on Gen3 this
is thus far always zero. Split the tables so the RMSTPCR can be set
too.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Extract the macros specific to Gen3 clock into a separate header.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Not all SoCs have the same PLL configuration options,
so make those PLL configuraion tables per-SoC.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Not all drivers use the same IDs, so make those IDs per-driver.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Split the massive driver into smaller per-SoC drivers and pull the
common code into a separate file. This would allow configuring out
unnecessary clock drivers once the Kconfig changes are in and also
allow adding more clock tables easily.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add support for RZ/A1 series SoCs.
Signed-off-by: NChris Brandt <chris.brandt@renesas.com>

Use the common RCAR_GEN2 config option instead of enumerating
each SoC and having a lengthy ifdef clause. No functional change.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Replace fdtdec_get_addr() with devfdt_get_addr() as the later one is
the current recommended practice.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Convert these configuration options to Kconfig, update board defconfigs
and drop them from whitelist.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Pull out u-boot extras into dtsi files to make synchronization of DTS
from Linux kernel as easy as a simple copy. All the U-Boot extras are
now in *-u-boot.dts* files instead.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.14,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . This includes both M3
and H3 ULCB and Salvator-X boards.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add macro QIXIS_LBMAP_EMMC, QIXIS_LBMAP_IFC, QIXIS_RCW_SRC_IFC,
QIXIS_RCW_SRC_EMMC to enable IFC and eMMC as boot sources for
qixis commands.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
[YS: Modify subject and add commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Currently only SD, NAND can be secondary boot sources controlled
by FPGA/CPLD via qixis commands. For SoC like LS1088 IFC-NOR
can be secondary boot source, while QSPI-NOR is the primary.
Add options in qixis to switch to other boot sources including
ifc and emmc.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The hash command function were not flushing the dcache before passing data
to CAAM/DMA and not invalidating the dcache when getting data back.

Due the data cache incoherency, HW accelerated hash commands used to fail
with CAAM errors like "Invalid KEY Command".

Check if pbuf and pout buffers are properly aligned to the cache line size
and flush/invalidate the memory regions to address this issue.

This solution is based in a previous work from Clemens Gruber in
commit 598e9dcc ("crypto/fsl: fix BLOB encapsulation and
decapsulation")
Reported-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NBreno Lima <breno.lima@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The current GPL only licensing on the device trees makes it very
impractical for other software components licensed under another
license.

To make it easier to reuse them, re-license the the device trees for
Freescale (now NXP) SoCs and boards under GPLv2+/X11 dual license.

Same trend is followed in linux.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: NPankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enables and compiles VID specific functions for SPL.
Signed-off-by: NPankit Garg <pankit.garg@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adds the support for VID on LS1088AQDS and LS1088ARDB systems.
It reads the fusesr register and changes the VDD accordingly by adjusting
the voltage via LTC3882 regulator.

This patch also takes care of the special case of 0.9V VDD is present in
fusesr register. In that case,it also changes the SERDES voltage by
disabling the SERDES, changing the SVDD and then re-enabling SERDES.
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NAmrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds a VID specific API in init_sequence_f and spl code flow
namely init_func_vid which is required to adjust core voltage.

VID specific code is required in spl, hence moving flag CONFIG_VID
out of spl flags.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When VID feature is supported, check the contents of fuse register
and configure DDR operate at 0.9v.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Restructures common driver to support LTC3882 voltage regulator
chip.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds below LTC3882 voltage regulator config:
CONFIG_VOL_MONITOR_LTC3882_READ
CONFIG_VOL_MONITOR_LTC3882_SET
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Moves IR chip (IR36021) specific code in flag to resolve
compilation issue where it is not present. For example,
LS1088A is having a new LTC3882 voltage chip.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds a board specific API namely board_adjust_vdd which
is required to define the board VDD adjust settings.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds below voltage values supported by LS1088A Soc:
1.025V(default), 0.9875V, 0.9750V, 0.9V, 1.0V, 1.0125V, 1.0250V.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Patch queue for efi - 2018-01-23

This time around we have a lot of EFI patches from Heinrich.
Highlights are:

  - Allow EFI applications to register as drivers
  - Allow exposure of U-Boot block devices from an EFI payload
  - Compatibility improvements

This reverts commit 998ae287.

This continues to fail in travis itself, so remove for now.
Signed-off-by: NTom Rini <trini@konsulko.com>

This converts the following to Kconfig:
   CONFIG_SOC_DA8XX
   CONFIG_SOC_DA850
   CONFIG_DA850_LOWLEVEL
   CONFIG_MACH_DAVINCI_DA850_EVM
   CONFIG_SYS_DA850_PLL_INIT
   CONFIG_SYS_DA850_DDR_INIT
Signed-off-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NDavid Lechner <david@lechnology.com>
[trini: Rework CONFIG_SYS_DA850_PLL_INIT so it's selected on SOC_DA8XX]
Signed-off-by: NTom Rini <trini@konsulko.com>

Some messages are only useful if an error occurs.
Fix a use after free.
Add a missing free.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Create device path nodes for UCLASS_ETH udevices.
Create device path nodes of block device children of UCLASS_MMC udevices.
Consistently use debug for unsupported nodes.
Set the log level to error.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: Fix build failure by adding #ifdef CONFIG_DM_ETH]
Signed-off-by: NAlexander Graf <agraf@suse.de>