This is needed for the upcoming ethernet DM conversion of the maxbcm
board. The configuration of the PHY is then extracted from the DT
instead of using the defines from the config header.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch enables the DM support for the SPI driver and the
SPI NOR flash chips. Some MVEBU boards boot from SPI NOR, so
adding the aliases and enabling CONFIG_DM_SEQ_ALIAS is needed
here.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Simon Glass <sjg@chromium.org>

This patch adds full DM support to the SPL on MVEBU. Currently
only serial is supported. Other drivers will follow.

This patch also adds the necessary config values for the DEBUG UART
to the MVEBU defconfig files. This came in handy while implementing
this DM support.

Additionally, the mvebu specific SPL linker script is removed and
this common one is used instead:

   arch/arm/cpu/u-boot-spl.lds

This common linker script already handles all special cases. No need
to reinvent the wheel for MVEBU here.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Simon Glass <sjg@chromium.org>

By using the common timer functions for mvebu/kirkwood we can get rid of quite
a lot of code.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>

Add qspi memory map address to device tree.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

In U-Boot most flashes uses "spi-flash" as compatible to bind the
device to flash driver, so adding "spi-flash" compatible to
m25p80 node.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

In U-Boot most flashes uses "spi-flash" as compatible to bind the
device to flash driver, so adding "spi-flash" compatible to
m25p80 node.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

In U-Boot most flashes uses "spi-flash" as compatible to bind the
device to flash driver, so adding "spi-flash" compatible to
m25p80 node.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Add qspi memory map and control module register maps to device tree.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

add spi alias for qspi so that spi probes the device and driver
successfully.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Rather than using a new debug UART implementation, use the standard one
provided by U-Boot.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NThomas Chou <thomas@wytron.com.tw>

Adjust all Tegra boards to use driver model for Ethernet, now that the
required drivers are converted.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The ProXstream2/PH1-LD6b is integrated with a new IP for DDR PHY
which is not register-compatible with the former SoCs.
Add a new command to support the register dump of this IP.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

As mentioned in the log of commit 019df879 (ARM: uniphier: add
ProXstream2 and PH1-LD6b support), the DRAM init code was missing
for a long time.  Finally, here it is.  SPL works now.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These headers are only included locally in arch/arm/mach-uniphier/.
There is no reason to export them by putting in the mach/ directory.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This command shows the boot mode pins, so it would be more at home
in the boot-mode subdirectory.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This command shows the register dump of the DDR PHY, so it would be
more at home in the dram subdirectory.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These includes are not necessary.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

On these platforms we have many cases of boards that enable device model
and GPIO support but do not enable OF_CONTROL and pass in a device tree
with the binary.  We need to bring in the platform data here as well.

Tested on Beaglebone Black.
Reported-by: NRobert Nelson <robertcnelson@gmail.com>
Reported-by: NFrancisco Aguerre <franciscoaguerre@gmail.com>
Reported-by: NJason Kridner <jkridner@beagleboard.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

Check for bmode before reading the boot device
to check if a serial downloader is started,
and returns UART if the serial downloader is set,
letting SPL to wait for an image if
CONFIG_SPL_YMODEM_SUPPORT is set.

This allows to load again a SPL based board
with imx_usb_loader together with a tool
such as kermit.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Fabio Estevam <Fabio.Estevam@freescale.com>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: NEric Nelson <eric@nelint.com>
Tested-by: NEric Nelson <eric@nelint.com>

For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.

For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.

Example:
void mxs_power_setup_dcdc_clocksource(void)
{
    mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}
Signed-off-by: NMichael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marex@denx.de>

Drop duplicated debug info for tcl.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

Make sure the NAND reset is not asserted in full U-Boot.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

If the system boots from NAND, make sure to de-assert the NAND IP
reset, otherwise the system will get stuck.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Define the NAND reset bit and fix the ordering of the macros.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

When we want to boot Linux with a DTB file downloaded from a TFTP
server or somewhere, we need to know the file name to be downloaded.

Assume the U-Boot configuration is shared among some similar boards.
If they are similar enough, the difference only appears in device
trees.  The build procedure would be like this:

 - Board A:  make foo_common_defconfig && make DEVICE_TREE=foo_board_a
 - Board B:  make foo_common_defconfig && make DEVICE_TREE=foo_board_b
 - Board C:  make foo_common_defconfig && make DEVICE_TREE=foo_board_c

In this case, the U-Boot image contains nothing about the DTB file name
it is running with.  (CONFIG_DEFAULT_DEVICE_TREE is not helpful for this
purpose because it is painful to change it from "make menuconfig" for
each board.)

This commit allows to lookup the DTB file name based on the compatible
string and set it to "fdt_file" environment.  Then "tftpboot $fdt_file"
will download the file we want.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The UMC (Universal Memory Controller) and the DDR PHY block are
highly related to each other.  It is better to have both code in the
same directory.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Both "Model 1" and "Model 2" are supported for ProXstream2 and
PH1-LD6b boards.  It is useful to show the model number in the
boot banner.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These are new SoCs from Socionext Inc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Compile this file for U-Boot proper as well as SPL, so that the
U-Boot proper can call uniphier_get_board_param().
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The DDR3 memory chips on ProXstream2 boards support up to 2133 MHz,
while only up to 1866MHz on PH1-LD6b boards.

Split the board data structure and change the DDR frequency of
ProXstream2 boards to 2133 MHz.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move "gd->fdt_blob" from the caller to the callee so that this
function can be used more easily.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

We sometimes have to implement different code depending on the SoC
revision.  This commit adds functions to get the model/revision
number.

Note:
  Model number: incremented on major changes of the SoC
  Revision number: incremented on minor changes of the SoC

The "Model 2" exists for PH1-sLD3, ProXstream2/PH1-LD6b.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Sync device trees with Linux.

Linux commit: 06ff6b2d63210922a1b1d0f4997e29ce75b5e0c0
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These nodes are not parsed by U-Boot for now, but syncing device trees
with Linux is helpful for easier diffing.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

UniPhier SoCs (except PH1-sLD3) have several nodes in common.
Factor out them into uniphier-common32.dtsi.  This improves the code
maintainability.

PH1-sLD3 is so old that it has more or less different register maps
than the others.  So, it cannot be included in this refactoring.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Return different error code depending on the reason so that the
caller can know the cause of the failure.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The bit 27-24 of the DTCR register is described as RANKEN in the
DDR PHY databook.  Follow this abbreviation.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>