This patch is only a temporarily workaround for crash introduced by
commit ac9cd480 ("bootstage: Correct relocation algorithm").

The crash occurs because the bootstage struct is not correctly aligned
when BOOTSTAGE feature is activated.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Acked-by: NPatrick Delaunay <patrick.delaunay@st.com>

Activate by default the command CLS (clear screen);
this command used in pxe or sysboot command (DISTRO support)
when the "menu background" keyword is present.

This patch avoid the warning "Unknown command 'cls'"
with extlinux.conf:

# Generic Distro Configuration file generated by OpenEmbedded
menu title Select the boot mode
MENU BACKGROUND /splash.bmp
TIMEOUT 20
DEFAULT stm32mp157c-ev1-emmc
LABEL stm32mp157c-ev1-emmc
	KERNEL /uImage
	FDT /stm32mp157c-ev1.dtb
	APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200

  ...
  Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf
  614 bytes read in 36 ms (16.6 KiB/s)
  Retrieving file: /splash.bmp
  46180 bytes read in 40 ms (1.1 MiB/s)
  Unknown command 'cls' - try 'help'
  Select the boot mode
  1:	stm32mp157c-ev1-sdcard
  ...
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Acked-by: NPatrick Delaunay <patrick.delaunay@st.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

- Assorted minor fixes

Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to
dra7xx_evm_defconfig.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>

With commit 37db55b7 ("linux/types.h: fix typo unchar") we have a
duplicate typedef for uchar. As linux/types.h is included in common.h we
don't need another typedef for uchar there.

Fixes: 37db55b7 ("linux/types.h: fix typo unchar")
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

Describe that a signature node can be added to a binary device tree using
the mkimage tool.

Provide an example device tree node.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Boris' email address has changed. Copy two entries from the Linux .mailmap
file.

Boris confirmed the new email address:
https://lists.denx.de/pipermail/u-boot/2019-December/393774.html

Cc: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Commit 656d8da9 (doc: Remove duplicated documentation directory) got
rid of most of Documentation/. But there's still an obviously useless
.gitignore left behind.

Also, there's a copy of the linux kernel's net/ethernet.txt binding
imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So
replace the latter by the former, and making Documentation/ finally
empty.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

commit 3b3e8a37
("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id")

did sync with recent linux kernel and replaced therefore the 'phy_id'
property with a phy-handle pointing to the mdio.

This is OK for linux, but introduces trouble with the already running
vxWorks on this target.

So this commit here re-inerts the phy_id property beside the phy-handle
property to be compatible with both.
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>

- fix DRAM bank detection for unified binary
- fix 32bit RPi4 config

i2c bugfixes for 2020.01
- i2c: i2c_cdns: fix write timeout on fifo boundary
  fixes timout issue when writting number of bytes is multiple
  of the FIFO depth.

- First set of u-boot-atmel fixes for 2020.01 cycle:
  This set includes a small fix for gpio bank names, one for removing
  unused headers (also touches some other boards), and a fix for the QSPI
  env read on one of the boards.

The rpi_4_32b_defconfig states that only one DRAM bank is present. This
leads to a wrong configuration of the available DRAM. Fix this by
setting the DRAM bank config accordingly.

Fixes: 193279d7 ("RPI: Add defconfigs for rpi4 (32/64)")
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

Up to now we only update the DRAM banks when we are define
CONFIG_BCM2711. But our one binary approach uses a config that supports
BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on
Raspberry Pi 4, even if it has more RAM.
Fix this by calling dram_init_banksize.

Fixes: 56940906 ("ARM: defconfig: add unified config for RPi3 and RPi4")
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

To update the dram bank information from device-tree we use
fdtdec_decode_ram_size() which expectes the the size-cells and
address-cells to be defined in the memory node. For normal system RAM
these values are defined in the root node. When the values differ from
the default values defined in the spec, we can end up with wrong RAM
bank information.

Switch to the "standard" way to update the RAM bank information to
avoid this.

Fixes: 9de5b89e ("rpi4: enable dram bank initialization")
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).

Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.

In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.

Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.
Signed-off-by: NMichael Auchter <michael.auchter@ni.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- fix crash and board reset when drawing RLE8 bitmaps
  bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
  (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
   stm32f746-disco, stm32f769-disco and wandboard)

In the initial SPI flash setup, the default bus mode being used was 3,
which is incorrect, causing a CRC error when the ENV was being read from
QSPI. Setting the default bus mode to 0 which is the correct mode.
Signed-off-by: NSwapna Gurumani <swapna.gurumani@microchip.com>

- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.

At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.

To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.
Reported-by: NRick Chen <rick@andestech.com>
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NRick Chen <rick@andestech.com>
Tested-by: NRick Chen <rick@andestech.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.

As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NRick Chen <rick@andestech.com>
Tested-by: NRick Chen <rick@andestech.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NRick Chen <rick@andestech.com>

OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.

Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.

The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").
Reported-by: NRick Chen <rick@andestech.com>
Suggested-by: NAnup Patel <Anup.Patel@wdc.com>
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NRick Chen <rick@andestech.com>
Tested-by: NRick Chen <rick@andestech.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

Add descriptions about U-Boot SPL feature and how to build and run.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

Those are required for cfi-flash driver to get correct address information.
Also modify size description correctly.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

Add CPU2 and CPU3 information in cpus node
to support four cores SMP booting.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

Fix two wrong settings of andes plic driver as below:

1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
   int can help to fix wrong plic enabling setting in RV64.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.

With ae350_rv[32|64]_spl_defconfigs:

U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.

With ae350_rv[32|64]_spl_xip_defconfigs:

U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.

Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>

This would help to make the necessary changes in drivers and device trees
in U-Boot tree itself. This feature would also be helpful to not pass
dtb during opensbi builds.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Signed-off-by: NRick Chen <rick@andestech.com>

Sync the hifive-unleashed-a00 dts from Linux with
below commit details:

commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive
Unleashed: add default chosen/stdout-path")

Idea is to periodically sync the dts from Linux instead of
tweaking internal changes one after another, so better not
add any intermediate changes in between. This would help to
maintain the dts files easy and meaningful since we are
reusing device tree files from Linux.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

This fixes a problem, where booting Linux using distro boot will
sometimes lead to an invalid instruction exception on the main hart. The
secondary harts are not affected and boot Linux successfully. The root
cause of this problem is a stack overflow on the main hart.

With distro boot, the current default stack size of 8KiB on RISC-V is
not sufficient and will cause a stack overflow. The stacks are allocated
sequentially. In the case of a stack overflow the stack of the main hart
can reach into that of another hart and be corrupted.

The stack overflow previously did not cause any problems, because only
stack frames, which are not used anymore since the hart enters Linux,
were corrupted. Starting with GCC 9, the stack usage has decreased. Now,
only the most recent stack frame overflows into the stack of a secondary
hart and is corrupted. The illegal instruction exception is caused by
the secondary hart overwriting the return address in the stack frame of
the main hart with an address that does not include valid code.

Increase the default stack size of each hart to 16KiB to avoid this
problem.
Reported-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: NDavid Abdurachmanov <david.abdurachmanov@sifive.com>
Tested-by: NAurelien Jarno <aurelien@aurel32.net>
Reviewed-by: NRick Chen <rick@andestech.com>

The commit 1b42ab3e ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.

The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>