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  1. 19 2月, 2014 1 次提交
  3. 18 2月, 2014 3 次提交
  5. 14 2月, 2014 2 次提交
  7. 13 2月, 2014 13 次提交
  9. 11 2月, 2014 2 次提交
  11. 10 2月, 2014 2 次提交
  13. 08 2月, 2014 9 次提交
  15. 07 2月, 2014 8 次提交
    • S
      mmc: Enabled quirk SDHCI_QUIRK_BROKEN_R1B · f9ec45d1
      由 Siva Durga Prasad Paladugu 提交于 
      As per the below commit
"mmc: sdhci: add the quirk for broken r1b response"
(sha1: 3a638320)
need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the
response type is R1b.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>
      f9ec45d1
    • R
      MMC: DWMMC: Correct the CLKDIV register value · d3e016cc
      由 Rajeshwari S Shinde 提交于 
      This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)

Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.

This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>
      d3e016cc
    • S
      mmc: set rca to 1 for MMC cards · def816a2
      由 Stephen Warren 提交于 
      U-Boot currently sets MMC cards' RCA register to 0. This value is
reserved according to the specification. Use a value of 1 instead, just
like the Linux kernel.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>
      def816a2
    • T
      x600: Switch to CONFIG_PHYLIB · 1a78d28d
      由 Tom Rini 提交于 
      Now that the designware ethernet driver uses phylib we need to turn it
on here.
Acked-by: NStefan Roese <sr@denx.de>
Signed-off-by: NTom Rini <trini@ti.com>
      1a78d28d
    • A
      net/designware: make driver compatible with data cache · 50b0df81
      由 Alexey Brodkin 提交于 
      Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:

 * Flush Tx/Rx buffer descriptors their modification
 * Invalidate Tx/Rx buffer descriptors before reading its values
 * Flush cache for data passed from CPU to GMAC
 * Invalidate cache for data passed from GMAC to CPU

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      50b0df81
    • A
      net/designware - switch driver to phylib usage · 92a190aa
      由 Alexey Brodkin 提交于 
      With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
 * Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
 * Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
 * Support of custom phy initialization is now done with existing
"board_phy_config".

Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.

For example:
 * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
 * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used

I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      92a190aa
    • A
      net: execute "miiphy_init" if CONFIG_PHYLIB defined · 27ee59af
      由 Alexey Brodkin 提交于 
      In "common/Makefile" "miiphyutil.o" gets built if any of the following
items enabled:
 * CONFIG_PHYLIB
 * CONFIG_MII
 * CONFIG_CMD_MII

So it's possible to not define CONFIG_MII or CONFIG_CMD_MII and still
use functions like "miiphy_get_dev_by_name".

In its turn "miiphy_get_dev_by_name" traverses "mii_devs" list which is
not initialized because "miiphy_init" never got called.

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      27ee59af
    • A
      net/designware: add explicit reset of {tx|rx}_currdescnum · 74cb708d
      由 Alexey Brodkin 提交于 
      Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".

In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.

So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      74cb708d