If BUILD_TAG is part of KBUILD_CFLAGS, then any time the value changes,
all files get rebuilt. In a continuous integration environment, the value
will change every build. This wastes time, assuming that incremental
builds would otherwise occur.

To solve this, remove BUILD_TAG from KBUILD_CFLAGS and add it to CFLAGS
for just the one file that uses it. This does have the disadvantage that
if any other files want to use the flag, we'll need to duplicate this
custom CFLAGS setup logic. However, it seems unlikely we'll need this.

An alternative would be to add BUILD_TAG to the "local version" and remove
the special case code from display_options.c. However, that would affect
the format of the U-Boot signon message, which may negatively affect
people looking for specific data there. The approach of using
file-specific CFLAGS was suggested by Masahiro Yamada.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NSimon Glass <sjg@chromium.org>

With the recent addition of UBI support, this patch will add the preset
parameters to allow for mouting an UBIFS from the 'fs' partition in NAND.

-V2: ubi.mtd=fs instead of ubi.mtd=4
Signed-off-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

CONFIG_SF_DEFAULT_MODE is used to select default SPI mode when using
sf commands. Therefore fix am43xx to use CONFIG_SF_DEFAULT_MODE instead
of CONFIG_DEFAULT_SPI_MODE.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

According to Data Manual(SPRS915P) of AM572x, TI QSPI controller on
DRA74 EVM(rev 1.1+) can support up to 64MHz in MODE-0, whereas MODE-3 is
limited to 48MHz. Hence, switch to MODE-0 for better throughput.
Also, add IODelay parameters for the same.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>

Fixes typo of pxe_addr_r with pxefile_addr_r.
Signed-off-by: NVagrant Cascadian <vagrant@debian.org>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>

I will take this over from Peter Barada, since I work with it daily
at Logic PD.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Acked-by: NPeter Barada <peter.barada@logicpd.com>

Based on the work done by Overo, this seems to help some compilers
that have a hard time fitting all the code into the allocated space.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Boot with the Linux zImage and am3517-evm.dtb pair, when SD/MMC media
is present. This behavior can be overridden by creating a 'uEnv.txt'
file with 'uenvcmd' defined.

To boot an existing 'uImage', create the following 'uEnv.txt':

[start]-----------------------------------------------------------------

loaduimage=fatload mmc 0:1 ${loadaddr} ${bootfile}
uenvcmd=run loaduimage; run mmcargs; bootm ${loadaddr}

[end]-------------------------------------------------------------------

Inspired by similar patches, for other OMAP3 boards, from EEWiki
- https://github.com/eewiki/u-boot-patches/tree/master/v2016.01Signed-off-by: NDerald D. Woods <woods.technical@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Initial commit for PH1-Pro4 Ace and Sanji boards.

Note:
There are two variants for the Ace board in terms of the amount of
DDR memory; 1GB or 2GB.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is used for on-board inter-connection.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This board has an EEPROM connected to the I2C channel 0 of the SoC.
Its slave address is 0x54.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This environment define has been here to work around the LMB
allocation error introduced by commit 9c11135c ("image: fix
getenv_bootm_size() function").

It is no longer needed because the root cause was fixed by commit
0cb389dd ("image: fix getenv_bootm_size() function again").
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

It turned out that DDR channel 2 was not working on ProXstream2
Vodka board.  Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails.

Fixes: 93d92d46 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram
to build these commands.

Fixes: 93d92d46 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This header is no longer used.

This is the last file in arch/arm/mach-uniphier/include/mach/.
At last, I've succeeded in eliminating the mach directory.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now, all this driver does can be covered by the generic EHCI driver
(drivers/usb/host/ehci-generic.c).  UniPhier SoCs have switched to
use it.  Delete this driver rather than bothering to convert it to
Driver Model.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NMarek Vasut <marex@denx.de>

The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.

Since commit 4feefdcf ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.

We no longer need to stick to the dedicated driver.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This allows the EHCI driver to get clocks from device tree.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This block provides clock and reset control for MIO (Media I/O)
hardware blocks such as USB2.0, SD card, eMMC, etc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This block provides clock and reset control for peripherals such as
UART, I2C, IC card, etc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These are mainly used for controlling clocks and resets.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The USB boot code is too fat and complicated to be included in SPL
(at least for now).  So, it was implemented as a separate project
(what we call USB-loader).

The expected boot sequence is as follows:

  Boot ROM -> USB-loader -> SPL -> U-Boot proper

The USB-loader loads the SPL and U-Boot proper from a USB memory
onto the locked L2 cache.  Then, SPL needs to copy the U-Boot proper
to DRAM, so this mode looks like a NOR boot from the view of SPL.
However, we want to distinguish between (genuine) NOR boot and USB
boot in some places.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This function is for local use in the file.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

UniPhier SoCs are not equipped with dedicated on-chip SRAM.  Instead,
locked outer cache is used as RAM area during the early boot stage
where DRAM is not ready yet.  This effectively means MMU must be
always enabled while we are in SPL.

Currently, the SPL image for UniPhier SoCs contains the page table
statically defined at compile time.  It has been a burden because the
16KB page table occupies a quarter memory footprint of the 64KB SPL
image.

Finally, there is no more room to implement new features in SPL.
Setting aside the NOR boot mode, this issue can be solved by creating
the page table onto RAM at run time.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

No special reason for the current stack address 0x0ff08000.
Change it to 0x00100000 to simplify the init_page_table.

There are two types of SoCs in terms of the load address of SPL.

 [1] PH1-sLD3, PH1-LD4, PH1-sLD8
   SPL is loaded at 0x00040000-0x0004ffff
 [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b
   SPL is loaded at 0x00100000-0x0010ffff

The new stack area (0x000f8000-0x00100000) should be safe for all the
cases.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This enum is referenced from common/spl/spl.c.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since commit ad1ecd20 ("fdt: Build a U-Boot binary without device
tree") and commit 03c25bcd ("fdt: Build an SPL binary without
device tree"), we can use shorter file names for the output images.

The default configuration for UniPhier SoCs enables CONFIG_OF_SEPARATE
and CONFIG_SPL_OF_CONTROL.  In this case, spl/u-boot-spl.bin is the
same as spl/u-boot-spl-dtb.bin.  Likewise, u-boot.img is the same as
as u-boot-dtb.img.  So, this change of the flow has no impact.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Some of PH1-Pro4 boards are equipped with larger amount of DRAM than
the reference board.  Add UMC settings to support them.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is no longer working, so needs reworking.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The environment "bootm_low" is updated before the "bootz" command.
This is common for all the boot modes (NOR, NAND, TFTP, etc.), so
can be factored out.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Commit 25d4eb80 ("ARM: uniphier: add bootm_low environment")
missed to add "bootm_low" for FIT boot.  Set "bootm_low" to the
DRAM base address.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>